Altera Stratix V Advanced Systems - Manual (Page 29)

Chapter 5: Board Test System 5–11
Using the Board Test System
February 2013 Altera Corporation Stratix V Advanced Systems Development Kit
User Guide
The HSMC Tab
The HSMC tab allows you to perform loopback tests on HSMC ports. This test erases
FPGA1.
Figure 5–6 shows the HSMC tab.
1
You must have the loopback HSMC installed on the HSMC connector for this test to
work correctly. Otherwise, set the PMA setting tab to test internal loopback mode
(serial loopback = 1).
The following sections describe the controls on the HSMC tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
Figure 5–6. The HSMC Tab