Avago Technologies LSI53C896 User Manual

Avago Technologies Hardware

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DB14-000083-04

LSI53C896
PCI to Dual Channel
Ultra2 SCSI
Multifunction Controller

TECHNICAL

MANUAL

S e p t e m b e r 2 0 0 3

Version 3.3

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Table of contents

Document Outline

Chapter1 Introduction
1.1 General Description
- Figure1.1 Typical LSI53C896 System Application
- Figure1.2 Typical LSI53C896 Board Application
1.2 Benefits of Ultra2 SCSI
1.3 Benefits of LVDlink Technology
1.4 TolerANT® Technology
1.5 LSI53C896 Benefits Summary
- 1.5.1 SCSI Performance
- 1.5.2 PCI Performance
- 1.5.3 Integration
- 1.5.4 Ease of Use
- 1.5.5 Flexibility
- 1.5.6 Reliability
- 1.5.7 Testability
Chapter2 Functional Description
- Figure2.1 LSI53C896 Block Diagram
2.1 PCI Functional Description
- 2.1.1 PCI Addressing
- 2.1.2 PCI Bus Commands and Functions Supported
  - Table 2.1 PCI Bus Commands and Encoding Types
- 2.1.3 Internal Arbiter
- 2.1.4 PCI Cache Mode
  - Table 2.2 PCI Cache Mode Alignment
2.2 SCSI Functional Description
- 2.2.1 SCRIPTS Processor
- 2.2.2 Internal SCRIPTS RAM
- 2.2.3 64-Bit Addressing in SCRIPTS
- 2.2.4 Hardware Control of SCSI Activity LED
- 2.2.5 Designing an Ultra2 SCSI System
- 2.2.6 Prefetching SCRIPTS Instructions
- 2.2.7 Opcode Fetch Burst Capability
- 2.2.8 Load/Store Instructions
- 2.2.9 JTAG Boundary Scan Testing
- 2.2.10 SCSI Loopback Mode
- 2.2.11 Parity Options
- 2.2.12 DMA FIFO
  - Figure2.3 DMA FIFO Sections
- 2.2.13 Data Paths
  - Figure2.4 LSI53C896 Host Interface SCSI Data Paths
- 2.2.14 SCSI Bus Interface
- 2.2.15 Select/Reselect during Selection/Reselection
- 2.2.16 Synchronous Operation
  - Figure2.7 Determining the Synchronous Transfer Rate
- 2.2.17 Interrupt Handling
- 2.2.18 Interrupt Routing
  - Figure2.8 Interrupt Routing Hardware Using the LSI53C896
- 2.2.19 Chained Block Moves
  - Figure2.9 Block Move and Chained Block Move Instructions
2.3 Parallel ROM Interface
- Table 2.7 Parallel ROM Support
2.4 Serial EEPROM Interface
- 2.4.1 Default Download Mode
  - Table 2.8 Mode A Serial EEPROM Data Format
- 2.4.2 No Download Mode
2.5 Power Management
- Table 2.9 Power States
- 2.5.1 Power State D0
- 2.5.2 Power State D1
- 2.5.3 Power State D2
- 2.5.4 Power State D3
Chapter3 Signal Descriptions
- Figure3.1 LSI53C896 Functional Signal Grouping
3.1 Internal Pull-ups on LSI53C896 Signals
- Table 3.1 LSI53C896 Internal Pull-ups and Pull-downs
3.2 PCI Bus Interface Signals
- 3.2.1 System Signals
  - Table 3.2 System Signals
- 3.2.2 Address and Data Signals
  - Table 3.3 Address and Data Signals
- 3.2.3 Interface Control Signals
  - Table 3.4 Interface Control Signals
- 3.2.4 Arbitration Signals
  - Table 3.5 Arbitration Signals
- 3.2.5 Error Reporting Signals
  - Table 3.6 Error Reporting Signals
- 3.2.6 Interrupt Signals
  - Table 3.7 Interrupt Signals
- 3.2.7 SCSI Function A GPIO Signals
  - Table 3.8 SCSI Function A GPIO Signals
- 3.2.8 SCSI Function B GPIO Signals
  - Table 3.9 SCSI Function B GPIO Signals
3.3 SCSI Bus Interface Signals
- Table 3.10 SCSI Bus Interface Signals
- 3.3.1 SCSI Function A Signals
  - Table 3.11 SCSI Function A Signals
  - Table 3.12 SCSI Function A_SCTRL Signals
- 3.3.2 SCSI Function B Signals
  - Table 3.13 SCSI Function B Signals
  - Table 3.14 SCSI Function B_SCRTL Signals
3.4 Flash ROM and Memory Interface Signals
- Table 3.15 Flash ROM and Memory Interface Signals
3.5 Test Interface Signals
- Table 3.16 Test Interface Signals
3.6 Power and Ground Signals
- Table 3.17 Power and Ground Signals
3.7 MAD Bus Programming
- Table 3.18 Decode of MAD[3:1] Pins
Chapter4 Registers
4.1 PCI Configuration Registers
- Table 4.1 PCI Configuration Register Map
4.2 SCSI Registers
- Table 4.2 SCSI Register Map
- Table 4.3 Examples of Synchronous Transfer Periods and Rates for SCSI1
- Table 4.4 Example Transfer Periods and Rates for Fast SCSI-2, Ultra, and Ultra2
- Table 4.5 Maximum Synchronous Offset
- Table 4.6 SCSI Synchronous Data FIFO Word Count
4.3 64-Bit SCRIPTS Selectors
4.4 Phase Mismatch Jump Registers
Chapter5 SCSI SCRIPTS Instruction Set
5.1 SCSI SCRIPTS
- Figure5.1 SCRIPTS Overview
5.2 Block Move Instructions
- 5.2.1 First Dword
  - Figure5.2 Block Move Instruction – First Dword
- 5.2.2 Second Dword
  - Figure5.3 Block Move Instruction – Second Dword
- 5.2.3 Third Dword
  - Figure5.4 Block Move Instruction – Third Dword
5.3 I/O Instructions
- 5.3.1 First Dword
  - Figure5.5 First 32-Bit Word of the I/O Instruction
- 5.3.2 Second Dword
  - Figure5.6 Second 32-Bit Word of the I/O Instruction
5.4 Read/Write Instructions
- 5.4.1 First Dword
  - Figure5.7 Read/Write Instruction – First Dword
- 5.4.2 Second Dword
  - Figure5.8 Read/Write Instruction – Second Dword
- 5.4.3 Read-Modify-Write Cycles
- 5.4.4 Move to/from SFBR Cycles
  - Table 5.1 Read/Write Instructions
5.5 Transfer Control Instructions
- 5.5.1 First Dword
  - Figure5.9 Transfer Control Instructions – First Dword
- 5.5.2 Second Dword
  - Figure5.10 Transfer Control Instructions – Second Dword
- 5.5.3 Third Dword
  - Figure5.11 Transfer Control Instructions – Third Dword
5.6 Memory Move Instructions
- 5.6.1 First Dword
  - Figure5.12 Memory Move Instructions – First Dword
- 5.6.2 Read/Write System Memory from a SCRIPTS
- 5.6.3 Second Dword
  - Figure5.13 Memory Move Instructions – Second Dword
- 5.6.4 Third Dword
  - Figure5.14 Memory Move Instructions – Third Dword
5.7 Load/Store Instructions
- 5.7.1 First Dword
  - Figure5.15 Load/Store Instruction – First Dword
- 5.7.2 Second Dword
  - Figure5.16 Load/Store Instructions – Second Dword
Chapter6 Specifications
6.1 DC Characteristics
- Table 6.1 Absolute Maximum Stress Ratings
- Table 6.2 Operating Conditions
- Table 6.3 LVD Driver SCSI Signals – SD[15:0], SDP[1:0], SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/...
- Figure6.1 LVD Driver
- Table 6.4 LVD Receiver SCSI Signals – SD[15:0], SDP[1:0], SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SI...
- Figure6.2 LVD Receiver
- Table 6.5 A and B DIFFSENS SCSI Signals
- Table 6.6 Input Capacitance
- Table 6.7 Bidirectional Signals – GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4, MAD[7:0]1
- Table 6.8 Output Signals – MAS/[1:0], MCE/, MOE/_TESTOUT1, MWE/, TDO
- Table 6.9 Bidirectional Signals – AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PER...
- Table 6.10 Input Signals – CLK, GNT/, IDSEL, INT_DIR, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS
- Table 6.11 Output Signals – INTA, INTB, ALT_INTA, ALT_INTB, REQ/
- Table 6.12 Output Signal – SERR/
6.2 TolerANT Technology Electrical Characteristics
- Table 6.13 TolerANT Technology Electrical Characteristics for SE SCSI Signals
- Figure6.3 Rise and Fall Time Test Condition
- Figure6.4 SCSI Input Filtering
- Figure6.5 Hysteresis of SCSI Receivers
- Figure6.6 Input Current as a Function of Input Voltage
- Figure6.7 Output Current as a Function of Output Voltage
6.3 AC Characteristics
- Table 6.14 External Clock
- Figure6.8 External Clock
- Table 6.15 Reset Input
- Figure6.9 Reset Input
- Table 6.16 Interrupt Output
- Figure6.10 Interrupt Output
6.4 PCI and External Memory Interface Timing Diagrams
- 6.4.1 Target Timing
- 6.4.2 Initiator Timing
- 6.4.3 External Memory Timing
6.5 SCSI Timing Diagrams
- Table 6.39 Initiator Asynchronous Send
- Figure6.35 Initiator Asynchronous Send
- Table 6.40 Initiator Asynchronous Receive
- Figure6.36 Initiator Asynchronous Receive
- Table 6.41 Target Asynchronous Send
- Figure6.37 Target Asynchronous Send
- Table 6.42 Target Asynchronous Receive
- Figure6.38 Target Asynchronous Receive
- Table 6.43 SCSI-1 Transfers (SE 5.0 Mbytes)
- Table 6.44 SCSI-1 Transfers (Differential 4.17 Mbytes)
- Table 6.45 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
- Table 6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
- Table 6.47 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers...
- Table 6.48 Ultra SCSI HVD Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfer...
- Table 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Qu...
- Figure6.39 Initiator and Target Synchronous Transfer
6.6 Package Drawings
- Table 6.50 Alphanumeric List by Signal Name
- Table 6.51 Alphanumeric List by BGA Position
- Figure6.40 LSI53C896 329 BGA (Bottom View)
- Figure6.41 LSI53C896 329 BGA Mechanical Drawing (Sheet 1 of 2)
AppendixA Register Summary
- TableA.1 LSI53C896 Register Map
AppendixB External Memory Interface Diagram Examples
- FigureB.1 16 Kbyte Interface with 200 ns Memory
- FigureB.2 64 Kbyte Interface with 150 ns Memory
- FigureB.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Memory
- FigureB.4 512 Kbyte Interface with 150 ns Memory
Index
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