Avago Technologies LSI53C896 - Manual (Page 207)

SCSI Registers 4-95
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x4E
SCSI Test Two (STEST2)
Read/Write
SCE SCSI Control Enable 7
Setting this bit allows assertion of all SCSI control and
data lines through the
SCSI Output Control Latch (SOCL)
and SCSI Output Data Latch (SODL) registers regardless
of whether the LSI53C896 SCSI function is configured as
a target or initiator.
Note: Do not set this bit during normal operation because it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
ROF Reset SCSI Offset 6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. If a SCSI gross error occurs, set this
bit. This bit automatically clears itself after resetting the
synchronous offset.
DIF HVD or SE/LVD 5
Setting this bit allows the LSI53C896 SCSI function to
interface to external HVD transceivers. Clearing this bit
enables SE or LVD operation. Set this bit in the
initialization routine if the HVD pair interface is used.
SLB SCSI Loopback Mode 4
Setting this bit allows the LSI53C896 SCSI function to
perform SCSI loopback diagnostics. That is, it enables
the SCSI core to simultaneously perform as both the
initiator and the target.
SZM SCSI High Impedance Mode 3
Setting this bit places all the open drain 48 mA SCSI
drivers into a high impedance state. This is to allow
internal loopback mode operation without affecting the
SCSI bus.
7 6 5 4 3 2 1 0
SCE ROF DIF SLB SZM AWS EXT LOW
0 0 0 0 0 0 0 0