Avago Technologies LSI53C896 - Manual (Page 68)

2-40 Functional Description
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
2.2.15 Select/Reselect during Selection/Reselection
In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in the initiator
mode) tries to select a target and is reselected by another. The Select
SCRIPTS instruction has an alternate address to which the SCRIPTS
jumps when this situation occurs. The analogous situation for target
devices is being selected while trying to perform a reselection.
When a change in operating mode occurs, the initiator SCRIPTS should
start with a Set Initiator instruction, or the target SCRIPTS should start
with a Set Target instruction. The Selection and Reselection Enable bits
(
SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted
so that the LSI53C896 may respond as an initiator or as a target. If only
selection is enabled, the LSI53C896 cannot be reselected as an initiator.
There are also status and interrupt bits in the
SCSI Interrupt Status Zero (SIST0) and
SCSI Interrupt Enable Zero (SIEN0) registers, respectively, indicating
that the LSI53C896 has been selected (bit 5) and reselected (bit 4).
2.2.16 Synchronous Operation
The LSI53C896 can transfer synchronous SCSI data in both the initiator
and target modes. The
SCSI Transfer (SXFER) register controls both the
synchronous offset and the transfer period. It may be loaded by the CPU
before SCRIPTS execution begins, from within SCRIPTS using a
Table Indirect I/O instruction, or with a Read-Modify-Write instruction.
The LSI53C896 can receive data from the SCSI bus at a synchronous
transfer period as short as 25 ns, regardless of the transfer period that
sends data. The LSI53C896 can receive data at one-fourth of the divided
SCLK frequency. Depending on the SCLK frequency, the negotiated
transfer period, and the synchronous clock divider, the LSI53C896 can
send synchronous data at intervals as short as 25 ns for Ultra2 SCSI,
50 ns for Ultra SCSI, 100 ns for fast SCSI, and 200 ns for SCSI-1.
2.2.16.1 Determining the Data Transfer Rate
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C896. Following is a brief description of the bits.
Figure 2.7 illustrates the clock division factors used in each register, and
the role of the register bits in determining the transfer rate.