Avago Technologies LSI53C896 - Manual (Page 84)

2-56 Functional Description
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
required, a 7406 (high voltage open collector inverter), a MTD4P05, and
several passive components are also needed. The memory size and speed
is determined by pull-up resistors on the 8-bit bidirectional memory bus at
power-up. The LSI53C896 senses this bus shortly after the release of the
Reset signal and configures the
Expansion ROM Base Address register
and the memory cycle state machines for the appropriate conditions.
The external memory interface works with a variety of ROM sizes and
speeds. An example set of interface drawings is in
Appendix B, “External Memory Interface Diagram Examples.”
The LSI53C896 supports a variety of sizes and speeds of expansion
ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of
pins MAD[3:1] allows the user to define how much external memory is
available to the LSI53C896.
Table 2.7 shows the memory space
associated with the possible values of MAD[3:1]. The MAD[3:1] pins are
fully described in
Chapter 3, “Signal Descriptions.”
To use one of these configurations in a host adapter board design, put
4.7 k
Ω
pull-up resistors on the MAD pins corresponding to the available
memory space. For example, to connect to a 64 Kbyte external ROM,
use a pull-up on MAD[2]. If the external memory interface is not used,
MAD[3:1] should be pulled HIGH.
Note: There are internal pull-downs on all of the MAD bus signals.
Table 2.7 Parallel ROM Support
MAD[3:1] Available Memory Space
000 16 Kbytes
001 32 Kbytes
010 64 Kbytes
011 128 Kbytes
100 256 Kbytes
101 512 Kbytes
110 1024 Kbytes
111 No external memory present