Avago Technologies LSI53C896 User Manual
Page 163
SCSI Registers
4-51
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
4.If the SCSI Interrupt Pending bit is set, then read the
SCSI Interrupt Status Zero (SIST0)
or
SCSI Interrupt Status One (SIST1)
register to
determine the cause of the SCSI Interrupt and go
back to step 2.
5.If the SCSI Interrupt Pending bit is clear, and the DMA
Interrupt Pending bit is set, then write 0x00 value to
this register.
6.Read the
register to verify the
aborted interrupt and to see whether any other
interrupting conditions have occurred.
SRST
Software Reset
6
Setting this bit resets the LSI53C896 SCSI function. All
operating registers are cleared to their respective default
values and all SCSI signals are deasserted. Setting this
bit does not assert the SCSI RST/ signal. This reset does
not clear the ID Mode bit or any of the PCI configuration
registers. This bit is not self-clearing; it must be cleared
to clear the reset condition (a hardware reset also clears
this bit).
SIGP
Signal Process
5
SIGP is a R/W bit that is writable at any time, and polled
and reset using
. The SIGP bit
is used in various ways to pass a flag to or from a running
SCRIPTS instruction.
The only SCRIPTS instruction directly affected by the
SIGP bit is Wait For Selection/Reselection. Setting this bit
causes that instruction to jump to the alternate address
immediately. The instructions at the alternate jump address
should check the status of SIGP to determine the cause of
the jump. The SIGP bit is usable at any time and is not
restricted to the wait for selection/reselection condition.
SEM
Semaphore
4
The SCRIPTS processor may set this bit using a
SCRIPTS register write instruction. An external processor
may also set it while the LSI53C896 SCSI function is
executing a SCRIPTS operation. This bit enables the
SCSI function to notify an external processor of a
predefined condition while SCRIPTS are running. The