Freescale Semiconductor 56F8122 - Manual (Page 14)

56F8322 Techncial Data, Rev. 10.0
14 Freescale Semiconductor
Preliminary
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8322 and 56F8122 devices are organized into functional groups,
as detailed in
Table 2-1 and as illustrated in Figure 2-1 and Figure 2-2 . In Table 2-2 , each table row
describes the signal or signals present on a pin.
Note: See Table 1-1 for 56F8122 functional differences.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of Pins in Package
56F8322 56F8122
Power (V
DD
or V
DDA
) 5 5
Ground (V
SS
or V
SSA
) 5 5
Supply Capacitors & V
PP
1
1. The V
PP
input shares the IRQA input
2 2
PLL and Clock 2 2
Interrupt and Program Control 2 2
Pulse Width Modulator (PWM) Ports
2
2. Pins in this section can function as SPI #1 and GPIO.
7 —
Serial Peripheral Interface (SPI) Port 0
3
3. Pins in this section can function as SCI #1 and GPIO.
4 8
Quadrature Decoder Port 0
4
4. Alternately, can function as Quad Timer A pins or GPIO.
4 —
CAN Ports 2 —
Analog to Digital Converter (ADC) Ports 9 9
Timer Module Port C
5
5. Pins can function as SCI #0 and GPIO.
2 2
Timer Module Port A — 4
JTAG/Enhanced On-Chip Emulation (EOnCE) 4 4
Temperature Sense 6
6. Tied internally to ANA7
0 —
Dedicated GPIO — 5