Freescale Semiconductor MPC5200B User Manual
Mpc5200b users guide
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Table of contents
Document Outline
- MPC5200B Users Guide
- Chapter 1 Introduction
- 1.1 Overview
- 1.2 Architecture
- 1.2.1 Embedded e300 Core
- 1.2.2 BestComm I / O Subsystem
- 1.2.3 Controller Area Network ( CAN )
- 1.2.4 Byte Data Link Controller - Digital BDLC-D
- 1.2.5 System Level Interfaces
- 1.2.6 SDRAM Controller and Interface
- 1.2.7 Multi-Function External LocalPlus Bus
- 1.2.8 Power Management
- 1.2.9 Systems Debug and Test
- 1.2.10 Physical Characteristics
- Chapter 2 Signal Descriptions
- Chapter 3 Memory Map
- Chapter 4 Resets and Reset Configuration
- Chapter 5 Clocks and Power Management
- 5.1 Overview
- 5.2 Clock Distribution Module (CDM)
- 5.3 MPC5200B Clock Domains
- 5.4 Power Management
- 5.5 CDM Registers
- 5.5.1 CDM JTAG ID Number Register-MBAR + 0x0200
- 5.5.2 CDM Power On Reset Configuration Register-MBAR + 0x0204
- 5.5.3 CDM Bread Crumb Register-MBAR + 0x0208
- 5.5.4 CDM Configuration Register-MBAR + 0x020C
- 5.5.5 CDM 48MHz Fractional Divider Configuration Register-MBAR + 0x0210
- 5.5.6 CDM Clock Enable Register-MBAR + 0x0214
- 5.5.7 CDM System Oscillator Configuration Register-MBAR + 0x0218
- 5.5.8 CDM Clock Control Sequencer Configuration Register-MBAR + 0x021C
- 5.5.9 CDM Soft Reset Register-MBAR + 0x0220
- 5.5.10 CDM System PLL Status Register-MBAR + 0x0224
- 5.5.11 PSC1 Mclock Config Register-MBAR + 0x0228
- 5.5.12 PSC2 Mclock Config Register-MBAR + 0x022C
- 5.5.13 PSC3 Mclock Config Register-MBAR + 0x0230
- 5.5.14 PSC6 (IrDA) Mclock Config Register-MBAR + 0x0234
- Chapter 6 e300 Processor Core
- Chapter 7 System Integration Unit ( SIU )
- 7.1 Overview
- 7.2 Interrupt Controller
- 7.2.1 Block Description
- 7.2.2 Interface Description
- 7.2.3 Programming Note
- 7.2.4 Interrupt Controller Registers
- 7.2.4.1 ICTL Peripheral Interrupt Mask Register-MBAR + 0x0500
- 7.2.4.2 ICTL Peripheral Priority and HI / LO Select 1 Register -MBAR + 0x0504
- 7.2.4.3 ICTL Peripheral Priority and HI / LO Select 2 Register -MBAR + 0x0508
- 7.2.4.4 ICTL Peripheral Priority and HI / LO Select 3 Register -MBAR + 0x050C
- 7.2.4.5 ICTL External Enable and External Types Register -MBAR + 0x0510
- 7.2.4.6 ICTL Critical Priority and Main Interrupt Mask Register-MBAR + 0x0514
- 7.2.4.7 ICTL Main Interrupt Priority and INT / SMI Select 1 Register -MBAR + 0x0518
- 7.2.4.8 ICTL Main Interrupt Priority and INT / SMI Select 2 Register-MBAR + 0x051C
- 7.2.4.9 ICTL Perstat, MainStat, MainStat, CritStat Encoded Register-MBAR + 0x0524
- 7.2.4.10 ICTL Critical Interrupt Status All Register-MBAR + 0x0528
- 7.2.4.11 ICTL Main Interrupt Status All Register-MBAR + 0x052C
- 7.2.4.12 ICTL Peripheral Interrupt Status All Register-MBAR + 0x0530
- 7.2.4.13 ICTL Peripheral Interrupt Status All Register-MBAR + 0x0538
- 7.2.4.14 ICTL Main Interrupt Emulation All Register-MBAR + 0x0540
- 7.2.4.15 ICTL Peripheral Interrupt Emulation All Register-MBAR + 0x0544
- 7.2.4.16 ICTL IRQ Interrupt Emulation All Register-MBAR + 0x0548
- 7.3 General Purpose I / O ( GPIO )
- 7.3.1 GPIO Pin Multiplexing
- 7.3.2 GPIO Programmer’s Model
- 7.3.2.1 GPIO Standard Registers-MBAR + 0x0B00
- 7.3.2.1.1 GPS Port Configuration Register-MBAR + 0x0B00
- 7.3.2.1.2 GPS Simple GPIO Enables Register-MBAR + 0x0B04
- 7.3.2.1.3 GPS Simple GPIO Open Drain Type Register -MBAR + 0x0B08
- 7.3.2.1.4 GPS Simple GPIO Data Direction Register-MBAR + 0x0B0C
- 7.3.2.1.5 GPS Simple GPIO Data Output Values Register -MBAR + 0x0B10
- 7.3.2.1.6 GPS Simple GPIO Data Input Values Register -MBAR + 0x0B14
- 7.3.2.1.7 GPS GPIO Output-Only Enables Register -MBAR + 0x0B18
- 7.3.2.1.8 GPS GPIO Output-Only Data Value Out Register -MBAR + 0x0B1C
- 7.3.2.1.9 GPS GPIO Simple Interrupt Enable Register-MBAR + 0x0B20
- 7.3.2.1.10 GPS GPIO Simple Interrupt Open-Drain Emulation Register -MBAR + 0x0B24
- 7.3.2.1.11 GPS GPIO Simple Interrupt Data Direction Register -MBAR + 0x0B28
- 7.3.2.1.12 GPS GPIO Simple Interrupt Data Value Out Register -MBAR + 0x0B2C
- 7.3.2.1.13 GPS GPIO Simple Interrupt Interrupt Enable Register -MBAR + 0x0B30
- 7.3.2.1.14 GPS GPIO Simple Interrupt Interrupt Types Register -MBAR + 0x0B34
- 7.3.2.1.15 GPS GPIO Simple Interrupt Master Enable Register -MBAR + 0x0B38
- 7.3.2.1.16 GPS GPIO Simple Interrupt Status Register-MBAR + 0x0B3C
- 7.3.2.2 WakeUp GPIO Registers-MBAR + 0x0C00
- 7.3.2.2.1 GPW WakeUp GPIO Enables Register-MBAR + 0x0C00
- 7.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register -MBAR + 0x0C04
- 7.3.2.2.3 GPW WakeUp GPIO Data Direction Register-MBAR + 0x0C08
- 7.3.2.2.4 GPW WakeUp GPIO Data Value Out Register -MBAR + 0x0C0C
- 7.3.2.2.5 GPW WakeUp GPIO Interrupt Enable Register-MBAR + 0x0C10
- 7.3.2.2.6 GPW WakeUp GPIO Individual Interrupt Enable Register -MBAR + 0x0C14
- 7.3.2.2.7 GPW WakeUp GPIO Interrupt Types Register-MBAR + 0x0C18
- 7.3.2.2.8 GPW WakeUp GPIO Master Enables Register -MBAR + 0x0C1C
- 7.3.2.2.9 GPW WakeUp GPIO Data Input Values Register -MBAR + 0x0C20
- 7.3.2.2.10 GPW WakeUp GPIO Status Register-MBAR + 0x0C24
- 7.3.2.1 GPIO Standard Registers-MBAR + 0x0B00
- 7.4 General Purpose Timers ( GPT )
- 7.5 Slice Timers
- 7.6 Real-Time Clock
- 7.6.1 Real-Time Clock Signals
- 7.6.2 Programming Note
- 7.6.3 RTC Interface Registers-MBAR + 0x0800
- 7.6.3.1 RTC Time Set Register-MBAR + 0x0800
- 7.6.3.2 RTC Date Set Register-MBAR + 0x0804
- 7.6.3.3 RTC New Year and Stopwatch Register-MBAR + 0x0808
- 7.6.3.4 RTC Alarm and Interrupt Enable Register-MBAR + 0x080C
- 7.6.3.5 RTC Current Time Register-MBAR + 0x0810
- 7.6.3.6 RTC Current Date Register-MBAR + 0x0814
- 7.6.3.7 RTC Alarm and Stopwatch Interrupt Register-MBAR + 0x0818
- 7.6.3.8 RTC Periodic Interrupt and Bus Error Register-MBAR + 0x081C
- 7.6.3.9 RTC Test Register/Divides Register-MBAR + 0x0820
- Chapter 8 SDRAM Memory Controller
- 8.1 Overview
- 8.2 Terminology and Notation
- 8.3 Features
- 8.4 Functional Description
- 8.5 Operation
- 8.6 Programming the SDRAM Controller
- 8.7 Memory Controller Registers (MBAR+0x0100:0x010C)
- 8.8 Address Bus Mapping
- Chapter 9 LocalPlus Bus (External Bus Interface)
- 9.1 Overview
- 9.2 Features
- 9.3 Interface
- 9.4 Modes of Operation
- 9.5 Configuration
- 9.6 DMA (BestComm) Interface (SCLPC)
- 9.7 Programmer’s Model
- 9.7.1 Chip Select / LPC Registers-MBAR + 0x0300
- 9.7.1.1 Chip Select 0/Boot Configuration Register-MBAR + 0x0300
- 9.7.1.2 Chip Select 1 Configuration Register-MBAR + 0x0304
- 9.7.1.3 Chip Select Control Register-MBAR + 0x0318
- 9.7.1.4 Chip Select Status Register-MBAR + 0x031C
- 9.7.1.5 Chip Select Burst Control Register-MBAR + 0x0328
- 9.7.1.6 Chip Select Deadcycle Control Register-MBAR + 0x032C
- 9.7.2 SCLPC Registers-MBAR + 0x3C00
- 9.7.3 SCLPC FIFO Registers-MBAR + 0x3C40
- 9.7.3.1 LPC Rx / Tx FIFO Data Word Register-MBAR + 0x3C40
- 9.7.3.2 LPC Rx / Tx FIFO Status Register-MBAR + 0x3C44
- 9.7.3.3 LPC Rx / Tx FIFO Control Register-MBAR + 0x3C48
- 9.7.3.4 LPC Rx / Tx FIFO Alarm Register-MBAR + 0x3C4C
- 9.7.3.5 LPC Rx / Tx FIFO Read Pointer Register-MBAR + 0x3C50
- 9.7.3.6 LPC Rx / Tx FIFO Write Pointer Register-MBAR + 0x3C54
- 9.7.1 Chip Select / LPC Registers-MBAR + 0x0300
- Chapter 10 PCI Controller
- 10.1 Overview
- 10.2 PCI External Signals
- 10.2.1 PCI_AD[31:0] - Address/Data Bus
- 10.2.2 PCI_CBE[3:0] - Command/Byte Enables
- 10.2.3 PCI_DEVSEL - Device Select
- 10.2.4 PCI_FRAME - Frame
- 10.2.5 PCI_IDSEL - Initialization Device Select
- 10.2.6 PCI_IRDY - Initiator Ready
- 10.2.7 PCI_CLK - PCI Clock
- 10.2.8 PCI_PERR - Parity Error
- 10.2.9 PCI_RST - Reset
- 10.2.10 PCI_SERR - System Error
- 10.2.11 PCI_STOP - Stop
- 10.2.12 PCI_TRDY - Target Ready
- 10.3 Registers
- 10.3.1 PCI Controller Type 0 Configuration Space
- 10.3.1.1 Device ID/ Vendor ID Registers PCIIDR(R) -MBAR + 0x0D00
- 10.3.1.2 Status/Command Registers PCISCR(R/RW/RWC) -MBAR + 0x0D04
- 10.3.1.3 Revision ID/ Class Code Registers PCICCRIR(R) -MBAR + 0x0D08
- 10.3.1.4 Configuration 1 Register PCICR1(R/RW) -MBAR + 0x0D0C
- 10.3.1.5 Base Address Register 0 PCIBAR0(RW) -MBAR + 0x0D10
- 10.3.1.6 Base Address Register 1 PCIBAR1(RW) -MBAR + 0x0D14
- 10.3.1.7 CardBus CIS Pointer Register PCICCPR(RW) -MBAR + 0x0D28
- 10.3.1.8 Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)-MBAR + 0x0D2C
- 10.3.1.9 Expansion ROM Base Address PCIERBAR(R) -MBAR + 0x0D30
- 10.3.1.10 Capabilities Pointer (Cap_Ptr) PCICPR(R)-MBAR + 0x0D34
- 10.3.1.11 Configuration 2 Register PCICR2 (R/RW) -MBAR + 0x0D3C
- 10.3.2 General Control/Status Registers
- 10.3.2.1 Global Status/Control Register PCIGSCR(RW) -MBAR + 0x0D60
- 10.3.2.2 Target Base Address Translation Register 0 PCITBATR0(RW) -MBAR + 0x0D64
- 10.3.2.3 Target Base Address Translation Register 1 PCITBATR1(RW) -MBAR + 0x0D68
- 10.3.2.4 Target Control Register PCITCR(RW) -MBAR + 0x0D6C
- 10.3.2.5 Initiator Window 0 Base/Translation Address Register PCIIW0BTAR(RW)-MBAR + 0x0D70
- 10.3.2.6 Initiator Window 1 Base/Translation Address Register PCIIW1BTAR(RW) -MBAR + 0x0D74
- 10.3.2.7 Initiator Window 2 Base/Translation Address Register PCIIW2BTAR(RW) -MBAR + 0x0D78
- 10.3.2.8 Initiator Window Configuration Register PCIIWCR(RW) -MBAR + 0x0D80
- 10.3.2.9 Initiator Control Register PCIICR(RW) -MBAR + 0x0D84
- 10.3.2.10 Initiator Status Register PCIISR(RWC) -MBAR + 0x0D88
- 10.3.2.11 PCI Arbiter Register PCIARB(RW) -MBAR + 0x0D8C
- 10.3.2.12 Configuration Address Register PCICAR (RW) -MBAR + 0x0DF8
- 10.3.3 Communication Sub-System Interface Registers
- 10.3.3.1 Multi-Channel DMA Transmit Interface
- 10.3.3.1.1 Tx Packet Size PCITPSR(RW) -MBAR + 0x3800
- 10.3.3.1.2 Tx Start Address PCITSAR(RW) -MBAR + 0x3804
- 10.3.3.1.3 Tx Transaction Control Register PCITTCR(RW) -MBAR + 0x3808
- 10.3.3.1.4 Tx Enables PCITER(RW)-MBAR + 0x380C
- 10.3.3.1.5 Tx Next Address PCITNAR(R) -MBAR + 0x3810
- 10.3.3.1.6 Tx Last Word PCITLWR(R) -MBAR + 0x3814
- 10.3.3.1.7 Tx Bytes Done Counts PCITDCR(R) -MBAR + 0x3818
- 10.3.3.1.8 Tx Packets Done Counts PCITPDCR(R) -MBAR + 0x3820
- 10.3.3.1.9 Tx Status PCITSR(RWC) -MBAR + 0x381C
- 10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) -MBAR + 0x3840
- 10.3.3.1.11 Tx FIFO Status Register PCITFSR(R/RWC) -MBAR + 0x3844
- 10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) -MBAR + 0x3848
- 10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) -MBAR + 0x384C
- 10.3.3.1.14 Tx FIFO Read Pointer Register PCITFRPR(RW) -MBAR + 0x3850
- 10.3.3.1.15 Tx FIFO Write Pointer Register PCITFWPR(RW) -MBAR + 0x3854
- 10.3.3.2 Multi-Channel DMA Receive Interface
- 10.3.3.2.1 Rx Packet Size PCIRPSR(RW) -MBAR + 0x3880
- 10.3.3.2.2 Rx Start Address PCIRSAR (RW) -MBAR + 0x3884
- 10.3.3.2.3 Rx Transaction Control Register PCIRTCR(RW) -MBAR + 0x3888
- 10.3.3.2.4 Rx Enables PCIRER (RW) -MBAR + 0x388C
- 10.3.3.2.5 Rx Next Address PCIRNAR(R) -MBAR + 0x3890
- 10.3.3.2.6 Rx Last Word PCIRLWR(R) -MBAR + 0x3894
- 10.3.3.2.7 Rx Bytes Done Counts PCIRDCR(R) -MBAR + 0x3898
- 10.3.3.2.8 Rx Packets Done Counts PCIRPDCR(R) -MBAR + 0x38A0
- 10.3.3.2.9 Rx Status PCIRSR (R/sw1) -MBAR + 0x389C
- 10.3.3.2.10 Rx FIFO Data Register PCIRFDR(RW) -MBAR + 0x38C0
- 10.3.3.2.11 Rx FIFO Status Register PCIRFSR(R/sw1) -MBAR + 0x38C4
- 10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) -MBAR + 0x38C8
- 10.3.3.2.13 Rx FIFO Alarm Register PCIRFAR(RW) -MBAR + 0x38CC
- 10.3.3.2.14 Rx FIFO Read Pointer Register PCIRFRPR(RW) -MBAR + 0x38D0
- 10.3.3.2.15 Rx FIFO Write Pointer Register PCIRFWPR (RW) -MBAR + 0x38D4
- 10.3.3.1 Multi-Channel DMA Transmit Interface
- 10.3.1 PCI Controller Type 0 Configuration Space
- 10.4 Functional Description
- 10.5 PCI Arbiter
- 10.6 Application Information
- Chapter 11 ATA Controller
- 11.1 Overview
- 11.2 BestComm Key Features
- 11.3 ATA Register Interface
- 11.3.1 ATA Host Registers-MBAR + 0x3A00
- 11.3.1.1 ATA Host Configuration Register-MBAR + 0x3A00
- 11.3.1.2 ATA Host Status Register-MBAR + 0x3A04
- 11.3.1.3 ATA PIO Timing 1 Register-MBAR + 0x3A08
- 11.3.1.4 ATA PIO Timing 2 Register-MBAR + 0x3A0C
- 11.3.1.5 ATA Multiword DMA Timing 1 Register-MBAR + 0x3A10
- 11.3.1.6 ATA Multiword DMA Timing 2 Register-MBAR + 0x3A14
- 11.3.1.7 ATA Ultra DMA Timing 1 Register-MBAR + 0x3A18
- 11.3.1.8 ATA Ultra DMA Timing 2 Register-MBAR + 0x3A1C
- 11.3.1.9 ATA Ultra DMA Timing 3 Register-MBAR + 0x 3A20
- 11.3.1.10 ATA Ultra DMA Timing 4 Register-MBAR + 0x3A24
- 11.3.1.11 ATA Ultra DMA Timing 5 Register-MBAR + 0x3A28
- 11.3.1.12 ATA Share Count Register-MBAR + 0x3A2C
- 11.3.2 ATA FIFO Registers-MBAR + 0x3A00
- 11.3.2.1 ATA Rx / Tx FIFO Data Word Register-MBAR + 0x3A3C
- 11.3.2.2 ATA Rx / Tx FIFO Status Register-MBAR + 0x3A40
- 11.3.2.3 ATA Rx / Tx FIFO Control Register-MBAR + 0x3A44
- 11.3.2.4 ATA Rx / Tx FIFO Alarm Register-MBAR + 0x3A48
- 11.3.2.5 ATA Rx / Tx FIFO Read Pointer Register-MBAR + 0x3A4C
- 11.3.2.6 ATA Rx / Tx FIFO Write Pointer Register-MBAR + 0x3A50
- 11.3.3 ATA Drive Registers-MBAR + 0x3A00
- 11.3.3.1 ATA Drive Device Control Register-MBAR + 0x3A5C
- 11.3.3.2 ATA Drive Alternate Status Register-MBAR + 0x3A5C
- 11.3.3.3 ATA Drive Data Register-MBAR + 0x3A60
- 11.3.3.4 ATA Drive Features Register-MBAR + 0x3A64
- 11.3.3.5 ATA Drive Error Register-MBAR + 0x3A64
- 11.3.3.6 ATA Drive Sector Count Register-MBAR + 0x3A68
- 11.3.3.7 ATA Drive Sector Number Register-MBAR + 0x3A6C
- 11.3.3.8 ATA Drive Cylinder Low Register-MBAR + 0x3A70
- 11.3.3.9 ATA Drive Cylinder High Register-MBAR + 0x3A74
- 11.3.3.10 ATA Drive Device / Head Register-MBAR + 0x3A78
- 11.3.3.11 ATA Drive Device Command Register-MBAR + 0x3A7C
- 11.3.3.12 ATA Drive Device Status Register-MBAR + 0x3A7C
- 11.3.1 ATA Host Registers-MBAR + 0x3A00
- 11.4 ATA Host Controller Operation
- 11.5 Signals and Connections
- 11.6 ATA Interface Description
- 11.7 ATA Bus Background
- 11.8 ATA RESET / Power-Up
- 11.9 ATA I/O Cable Specifications
- Chapter 12 Universal Serial Bus ( USB )
- 12.1 Overview
- 12.2 Data Transfer Types
- 12.3 Host Controller Interface
- 12.4 Host Control ( HC ) Operational Registers
- 12.4.1 Programming Note
- 12.4.2 Control and Status Partition-MBAR + 0x1000
- 12.4.2.1 USB HC Revision Register-MBAR + 0x1000
- 12.4.2.2 USB HC Control Register-MBAR + 0x1004
- 12.4.2.3 USB HC Command Status Register-MBAR + 0x1008
- 12.4.2.4 USB HC Interrupt Status Register -MBAR + 0x 100C
- 12.4.2.5 USB HC Interrupt Enable Register-MBAR + 0x 1010
- 12.4.2.6 USB HC Interrupt Disable Register-MBAR + 0x 1014
- 12.4.3 Memory Pointer Partition-MBAR + 0x1018
- 12.4.3.1 USB HC HCCA Register-MBAR + 0x1018
- 12.4.3.2 USB HC Period Current Endpoint Descriptor Register -MBAR + 0x101C
- 12.4.3.3 USB HC Control Head Endpoint Descriptor Register -MBAR + 0x1020
- 12.4.3.4 USB HC Control Current Endpoint Descriptor Register -MBAR + 0x1024
- 12.4.3.5 USB HC Bulk Head Endpoint Descriptor Register-MBAR + 0x1028
- 12.4.3.6 USB HC Bulk Current Endpoint Descriptor Register-MBAR + 0x102C
- 12.4.3.7 USB HC Done Head Register-MBAR + 0x1030
- 12.4.4 Frame Counter Partition-MBAR + 0x1034
- 12.4.5 Root Hub Partition-MBAR + 0x1048
- Chapter 13 BestComm
- 13.1 Overview
- 13.2 BestComm Functional Description
- 13.3 Features summary
- 13.4 Descriptors
- 13.5 Tasks
- 13.6 Memory Map/ Register Definitions
- 13.7 Task Table (Entry Table)
- 13.8 Task Descriptor Table
- 13.9 Variable Table
- 13.10 Function Descriptor Table
- 13.11 Context Save Area
- 13.12 External DMA Request
- 13.13 External DMA Breakpoint
- 13.14 BestComm XLB Address Snooping
- 13.15 BestComm DMA Registers-MBAR + 0x1200
- 13.15.1 SDMA Task Bar Register-MBAR + 0x1200
- 13.15.2 SDMA Current Pointer Register-MBAR + 0x1204
- 13.15.3 SDMA End Pointer Register-MBAR + 0x1208
- 13.15.4 SDMA Variable Pointer Register-MBAR + 0x120C
- 13.15.5 SDMA Interrupt Vector, PTD Control Register-MBAR + 0x1210
- 13.15.6 SDMA Interrupt Pending Register-MBAR + 0x1214
- 13.15.7 SDMA Interrupt Mask Register-MBAR + 0x1218
- 13.15.8 SDMA Task Control 0 Register-MBAR + 0x121C
- 13.15.9 SDMA Task Control 2 Register-MBAR + 0x1220
- 13.15.10 SDMA Task Control 4 Register-MBAR + 0x1224
- 13.15.11 SDMA Task Control 6 Register-MBAR + 0x1228
- 13.15.12 SDMA Task Control 8 Register-MBAR + 0x122C
- 13.15.13 SDMA Task Control A Register-MBAR + 0x1230
- 13.15.14 SDMA Task Control C Register-MBAR + 0x1234
- 13.15.15 SDMA Task Control E Register-MBAR + 0x1238
- 13.15.16 SDMA Initiator Priority 0 Register-MBAR + 0x123C
- 13.15.17 SDMA Initiator Priority 4 Register-MBAR + 0x1240
- 13.15.18 SDMA Initiator Priority 8 Register-MBAR + 0x1244
- 13.15.19 SDMA Initiator Priority 12 Register-MBAR + 0x1248
- 13.15.20 SDMA Initiator Priority 16 Register-MBAR + 0x124C
- 13.15.21 SDMA Initiator Priority 20 Register-MBAR + 0x1250
- 13.15.22 SDMA Initiator Priority 24 Register-MBAR + 0x1254
- 13.15.23 SDMA Initiator Priority 28 Register-MBAR + 0x1258
- 13.15.24 SDMA Requestor MuxControl-MBAR + 0x125C
- 13.15.25 SDMA task Size0-MBAR + 0x1260
- 13.15.26 SDMA task 0 & task Size 1 map
- 13.15.27 SDMA Reserved Register 1-MBAR + 0x1268
- 13.15.28 SDMA Reserved Register 2-MBAR + 0x126C
- 13.15.29 SDMA Debug Module Comparator 1, Value 1 Register-MBAR + 0x1270
- 13.15.30 SDMA Debug Module Comparator 2, Value 2 Register-MBAR + 0x1274
- 13.15.31 SDMA Debug Module Control Register-MBAR + 0x1278
- 13.15.32 SDMA Debug Module Status Register-MBAR + 0x127C
- 13.16 On-Chip SRAM
- 13.17 Programming Model
- Chapter 14 Fast Ethernet Controller ( FEC )
- 14.1 Overview
- 14.2 Modes of Operation
- 14.3 I / O Signal Overview
- 14.4 FEC Memory Map and Registers
- 14.5 FEC Registers-MBAR + 0x3000
- 14.5.1 FEC ID Register-MBAR + 0x3000
- 14.5.2 FEC Interrupt Event Register-MBAR + 0x3004
- 14.5.3 FEC Interrupt Enable Register-MBAR + 0x3008
- 14.5.4 FEC Rx Descriptor Active Register-MBAR + 0x3010
- 14.5.5 FEC Tx Descriptor Active Register-MBAR + 0x3014
- 14.5.6 FEC Ethernet Control Register-MBAR + 0x3024
- 14.5.7 FEC MII Management Frame Register-MBAR + 0x3040
- 14.5.8 FEC MII Speed Control Register-MBAR + 0x3044
- 14.5.9 FEC MIB Control Register-MBAR + 0x3064
- 14.5.10 FEC Receive Control Register-MBAR + 0x3084
- 14.5.11 FEC Hash Register-MBAR + 0x3088
- 14.5.12 FEC Tx Control Register-MBAR + 0x30C4
- 14.5.13 FEC Physical Address Low Register-MBAR + 0x30E4
- 14.5.14 FEC Physical Address High Register-MBAR + 0x30E8
- 14.5.15 FEC Opcode / Pause Duration Register-MBAR + 0x30EC
- 14.5.16 FEC Descriptor Individual Address 1 Registe-MBAR + 0x3118
- 14.5.17 FEC Descriptor Individual Address 2 Register-MBAR + 0x311C
- 14.5.18 FEC Descriptor Group Address 1 Register-MBAR + 0x3120
- 14.5.19 FEC Descriptor Group Address 2 Register-MBAR + 0x3124
- 14.5.20 FEC Tx FIFO Watermark Register-MBAR + 0x3144
- 14.6 FIFO Interface
- 14.7 FEC Tx FIFO Data Register-MBAR + 0x31A4
- 14.8 FEC Tx FIFO Status Register-MBAR + 0x31A8
- 14.8.1 FEC Rx FIFO Control Register-MBAR + 0x318C
- 14.8.2 FEC Rx FIFO Last Read Frame Pointer Register-MBAR + 0x3190
- 14.8.3 FEC Rx FIFO Last Write Frame Pointer Register-MBAR + 0x3194
- 14.8.4 FEC Rx FIFO Alarm Pointer Register-MBAR + 0x3198
- 14.8.5 FEC Rx FIFO Read Pointer Register-MBAR + 0x319C
- 14.8.6 FEC Rx FIFO Write Pointer Register-MBAR + 0x31A0
- 14.8.7 FEC Reset Control Register-MBAR + 0x31C4
- 14.8.8 FEC Transmit FSM Register-MBAR + 0x31C8
- 14.9 Initialization Sequence
- 14.9.1 Hardware Controlled Initialization
- 14.9.2 User Initialization (Prior to Asserting ETHER_EN)
- 14.9.3 Frame Control/Status Words
- 14.9.4 Network Interface Options
- 14.9.5 FEC Frame Reception
- 14.9.6 Ethernet Address Recognition
- 14.9.7 Full-Duplex Flow Control
- 14.9.8 Inter-Packet Gap Time
- 14.9.9 Collision Handling
- 14.9.10 Internal and External Loopback
- 14.9.11 Ethernet Error-Handling Procedure
- Chapter 15 Programmable Serial Controller ( PSC)
- 15.1 Overview
- 15.2 PSC Registers-MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
- 15.2.1 Mode Register 1 (0x00)-MR1
- 15.2.2 Mode Register 2 (0x00) - MR2
- 15.2.3 Status Register (0x04) - SR
- 15.2.4 Clock Select Register (0x04) - CSR
- 15.2.5 Command Register (0x08)-CR
- 15.2.6 Rx Buffer Register (0x0C) - RB
- 15.2.7 Tx Buffer Register (0x0C)-TB
- 15.2.8 Input Port Change Register (0x10) - IPCR
- 15.2.9 Auxiliary Control Register (0x10) - ACR
- 15.2.10 Interrupt Status Register (0x14) - ISR
- 15.2.11 Interrupt Mask Register (0x14)-IMR
- 15.2.12 Counter Timer Upper Register (0x18)-CTUR
- 15.2.13 Counter Timer Lower Register (0x1C)-CTLR
- 15.2.14 Codec Clock Register (0x20)-CCR
- 15.2.15 AC97 Slots Register (0x24)-AC97Slots
- 15.2.16 AC97 Command Register (0x28)-AC97CMD
- 15.2.17 AC97 Status Data Register (0x2C)-AC97Data
- 15.2.18 Interrupt Vector Register (0x30)-IVR
- 15.2.19 Input Port Register (0x34)-IP
- 15.2.20 Output Port 1 Bit Set (0x38)-OP1
- 15.2.21 Output Port 0 Bit Set (0x3C)-OP0
- 15.2.22 Serial Interface Control Register (0x40)-SICR
- 15.2.23 Infrared Control 1 (0x44)-IRCR1
- 15.2.24 Infrared Control 2 (0x48)-IRCR2
- 15.2.25 Infrared SIR Divide Register (0x4C)-IRSDR
- 15.2.26 Infrared MIR Divide Register (0x50)-IRMDR
- 15.2.27 Infrared FIR Divide Register (0x54)-IRFDR
- 15.2.28 Rx FIFO Number of Data (0x58)-RFNUM
- 15.2.29 Tx FIFO Number of Data (0x5C)-TFNUM
- 15.2.30 Rx FIFO Data (0x60)-RFDATA
- 15.2.31 Rx FIFO Status (0x64)-RFSTAT
- 15.2.32 Rx FIFO Control (0x68)-RFCNTL
- 15.2.33 Rx FIFO Alarm (0x6E)-RFALARM
- 15.2.34 Rx FIFO Read Pointer (0x72)-RFRPTR
- 15.2.35 Rx FIFO Write Pointer(0x76)-RFWPTR
- 15.2.36 Rx FIFO Last Read Frame (0x7A)-RFLRFPTR
- 15.2.37 Rx FIFO Last Write Frame PTR (0x7C)-RFLWFPTR
- 15.2.38 Tx FIFO Data (0x80)-TFDATA
- 15.2.39 Tx FIFO Status (0x84)-TFSTAT
- 15.2.40 Tx FIFO Control (0x88)-TFCNTL
- 15.2.41 Tx FIFO Alarm (0x8E)-TFALARM
- 15.2.42 Tx FIFO Read Pointer (0x92)-TFRPTR
- 15.2.43 Tx FIFO Write Pointer (0x96)-TFWPTR
- 15.2.44 Tx FIFO Last Read Frame (0x9A)-TFLRFPTR
- 15.2.45 Tx FIFO Last Write Frame PTR (0x9C)-TFLWFPTR
- 15.3 PSC Operation Modes
- 15.3.1 PSC in UART Mode
- 15.3.2 PSC in Codec Mode
- 15.3.2.1 Block Diagram and Signal Definition for Codec Mode
- 15.3.2.2 Codec Clock and FrameSync Generation
- 15.3.2.3 Transmitting and Receiving in “Soft Modem” Codec Mode
- 15.3.2.4 Transmitting and Receiving in ESAI Mode (Enhanced Serial Audio Interface)
- 15.3.2.5 Transmitting and Receiving in “Cell Phone” Mode
- 15.3.2.6 Transmitting and Receiving in I2S Master Mode
- 15.3.2.7 Transmitting and Receiving in SPI Mode
- 15.3.3 PSC in AC97 Mode
- 15.3.4 PSC in IrDA mode
- 15.4 PSC FIFO System
- Chapter 16 XLB Arbiter
- 16.1 Overview
- 16.2 XLB Arbiter Registers-MBAR + 0x1F00
- 16.2.1 Arbiter Configuration Register (R/W)-MBAR + 0x1F40
- 16.2.2 Arbiter Version Register (R)-MBAR + 0x1F44
- 16.2.3 Arbiter Status Register (R/W)-MBAR + 0x1F48
- 16.2.4 Arbiter Interrupt Enable Register (R/W)-MBAR + 0x1F4C
- 16.2.5 Arbiter Address Capture Register (R)-MBAR + 0x1F50
- 16.2.6 Arbiter Bus Signal Capture Register (R)-MBAR + 0x1F54
- 16.2.7 Arbiter Address Tenure Time-Out Register (R/W)-MBAR + 0x1F58
- 16.2.8 Arbiter Data Tenure Time-Out Register (R/W)-MBAR + 0x1F5C
- 16.2.9 Arbiter Bus Activity Time-Out Register (R/W)-MBAR + 0x1F60
- 16.2.10 Arbiter Master Priority Enable Register (R/W)-MBAR + 0x1F64
- 16.2.11 Arbiter Master Priority Register (R/W)-MBAR + 0x1F68
- 16.2.12 Arbiter Snoop Window Register (RW)-MBAR + 0x1F70
- 16.2.13 Arbiter Reserved Registers-MBAR + 0x1F00-1F3C, 0x1F74-1FFF
- Chapter 17 Serial Peripheral Interface ( SPI )
- 17.1 Overview
- 17.2 SPI Signal Description
- 17.3 SPI Registers-MBAR + 0x0F00
- 17.3.1 SPI Control Register 1-MBAR + 0x0F00
- 17.3.2 SPI Control Register 2-MBAR + 0x0F01
- 17.3.3 SPI Baud Rate Register-MBAR + 0x0F04
- 17.3.4 SPI Status Register -MBAR + 0x0F05
- 17.3.5 SPI Data Register-MBAR + 0x0F09
- 17.3.6 SPI Port Data Register-MBAR + 0x0F0D
- 17.3.7 SPI Data Direction Register-MBAR + 0x0F10
- 17.4 Functional Description
- Chapter 18 Inter-Integrated Circuit ( I 2 C )
- 18.1 Overview
- 18.2 I2C Controller
- 18.3 I2C Interface Registers
- 18.3.1 I2C Address Register (MADR)-MBAR + 0x3D00 / 0x3D40
- 18.3.2 I2C Frequency Divider Register (MFDR)-MBAR + 0x3D04 / 0x3D44
- 18.3.3 I2C Control Register (MCR)-MBAR + 0x3D08 / 0x3D48
- 18.3.4 I2C Status Register (MSR)-MBAR + 0x3D0C / 0x3D4C
- 18.3.5 I2C Data I / O Register (MDR)-MBAR+ x3D10 / 0x3D50
- 18.3.6 I2C Interrupt Control Register-MBAR + 0x3D20
- 18.3.7 I2C Filter Register (MIFR)-MBAR + 0x3D24
- 18.4 Initialization Sequence
- 18.5 Transfer Initiation and Interrupt
- Chapter 19 Controller Area Network ( MSCAN )
- 19.1 Overview
- 19.2 Features
- 19.3 External Signals
- 19.4 CAN System
- 19.5 Memory Map / Register Definition
- 19.5.1 Module Memory Map
- 19.5.2 Register Descriptions
- 19.5.3 MSCAN Control Register 0 (CANCTL0)-MBAR + 0x0900 / 0x980
- 19.5.4 MSCAN Control Register 1 (CANCTL1)-MBAR + 0x0901 / 0x981
- 19.5.5 MSCAN Bus Timing Register 0 (CANBTR0)-MBAR + 0x0904 / 0x984
- 19.5.6 MSCAN Bus Timing Register 1 (CANBTR1)-MBAR + 0x0905 / 0x985
- 19.5.7 MSCAN Receiver Flag Register (CANRFLG)-MBAR+0x0908 / 0x988
- 19.5.8 MSCAN Receiver Interrupt Enable Register (CANRIER)-MBAR + 0x0909 / 0x989
- 19.5.9 MSCAN Transmitter Flag Register (CANTFLG)-MBAR + 0x090C / 0x98C
- 19.5.10 MSCAN Transmitter Interrupt Enable Register (CANTIER)-MBAR+0x090D / 0x098D
- 19.5.11 MSCAN Transmitter Message Abort Request (CANTARQ)-MBAR + 0x0910 / 0x0990
- 19.5.12 MSCAN Transmitter Message Abort Ack (CANTAAK)-MBAR +0x0911 / 0x0991
- 19.5.13 MSCAN Transmit Buffer Selection (CANTBSEL)-MBAR + 0x0914 /0x0991
- 19.5.14 MSCAN ID Acceptance Control Register (CANIDAC)-MBAR + 0x0915 / 0x0995
- 19.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C
- 19.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D
- 19.5.17 MSCAN ID Acceptance Registers (CANIDAR0-7)-MBAR + 0x0920 / 0x09A0
- 19.5.18 MSCAN ID Mask Register (CANIDMR0-7)-MBAR + 0x0928 / 0x09A8
- 19.6 Programmer’s Model of Message Storage
- 19.6.1 Identifier Registers (IDR0-3)
- 19.6.2 Data Segment Registers (DSR0-7)
- 19.6.3 Data Length Register (DLR)
- 19.6.4 MSCAN Transmit Buffer Priority Register (TBPR)-MBAR + 0x0979 / 0x09F9
- 19.6.5 MSCAN Time Stamp Register High (TSRH)-MBAR + 0x097C / 0x09FC
- 19.6.6 MSCAN Time Stamp Register Low (TSRL)-MBAR + 0x097D / 0x09FD
- 19.7 Functional Description
- 19.7.1 General
- 19.7.2 Message Storage
- 19.7.3 Identifier Acceptance Filter
- 19.7.4 Protocol Violation Protection
- 19.7.5 Clock System
- 19.7.6 Timer Link
- 19.7.7 Modes of Operation
- 19.7.8 Low Power Options
- 19.7.9 Description of Interrupt Operation
- 19.7.10 Interrupt Acknowledge
- 19.7.11 Recovery from STOP or WAIT
- Chapter 20 Byte Data Link Controller (BDLC)
- 20.1 Overview
- 20.2 Features
- 20.3 Modes of Operation
- 20.4 Block Diagram
- 20.5 Signal Description
- 20.6 Overview
- 20.7 Memory Map and Registers
- 20.7.1 Overview
- 20.7.2 Module Memory Map
- 20.7.3 Register Descriptions
- 20.7.3.1 BDLC Control Register 1 (DLCBCR1)-MBAR + 0x1300
- 20.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x1300
- 20.7.3.3 BDLC Control Register 2 (DLCBCR2) - MBAR + 0x1304
- 20.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x1305
- 20.7.3.5 BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0x1308
- 20.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309
- 20.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C
- 20.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D
- 20.8 Functional Description
- 20.9 Resets
- Chapter 21 Debug Support and JTAG Interface
- Appendix A Acronyms and Terms
- Appendix B List of Registers