Freescale Semiconductor MPC5200B - Manual (Page 746)

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MPC5200B Users Guide, Rev. 1
Freescale Semiconductor A-7
MAC/PHY . . . . . . . . . . . . . . Multiply-and-ACcumulate/Physical Layer Device
Master . . . . . . . . . . . . . . . . . . Name given to a bus device granted control, or mastership, of the bus.
MBAR. . . . . . . . . . . . . . . . . . Module Base Address Register
Mb, Mbit . . . . . . . . . . . . . . . . Megabit (written with lowercase b; 1024 Kilobits)
MB, MByte . . . . . . . . . . . . . . MegaByte (written with uppercase B; 1024 KiloBytes)
Mbps . . . . . . . . . . . . . . . . . . . Million bits per second
MBS . . . . . . . . . . . . . . . . . . . Maximum Burst Size
MC . . . . . . . . . . . . . . . . . . . . Memory Controller
MEMCTL . . . . . . . . . . . . . . . SDRAM Controller
Memory access ordering. . . . The specific order in which the processor performs load and store memory access and the order in which those
accesses complete.
Memory Controller . . . . . . . . A unit whose primary function is to control the external bus memories and I/O devices.
Memory coherency . . . . . . . . An aspect of caching in which it is ensured an accurate view of memory is provided to all devices sharing
system memory.
Memory consistency . . . . . . . Refers to agreement of levels of memory with respect to a single processor and system memory. For example,
on-chip cache, secondary cache, and system memory.
Microarchitecture . . . . . . . . . Hardware details of a microprocessor’s design. Such details are not defined by the PowerPC architecture.
MII . . . . . . . . . . . . . . . . . . . . Media-Independent Interface
mips. . . . . . . . . . . . . . . . . . . . million instructions per second
MIR. . . . . . . . . . . . . . . . . . . . Medium Infrared. See also FIR and SIR.
MMAP . . . . . . . . . . . . . . . . . Memory Map
MMU . . . . . . . . . . . . . . . . . . Memory Management Unit—a functional unit capable of translating an effective (logical) address to a
physical address, providing protection mechanisms, and defining caching methods.
Mnemonic . . . . . . . . . . . . . . . The abbreviated name of an instruction used for coding.
mod . . . . . . . . . . . . . . . . . . . . mode
Modified state . . . . . . . . . . . . When a cache block is in the modified state, it has been modified by the processor since it was copied from
memory. See also MESI.
MPC603e . . . . . . . . . . . . . . . a microprocessor—a low-power implementation of the PowerPC Reduced Instruction Set Computer (RISC)
architecture. The MPC603e microprocessor offers workstation-level performance packed into a low-power,
low-cost design ideal for desktop computers, notebooks and battery-powered systems, as well as printer and
imaging equipment, telecommunications systems, networking and communications infrastructure, industrial
controls, and home entertainment and educational devices.
Munging . . . . . . . . . . . . . . . . A modification performed on an effective address that allows it to appear to the processor that individual aligned
scalars are stored as Little-Endian values, when in fact it is stored in Big-Endian order, but at different byte
addresses within double words.
Note: Munging affects only the effective address and not the byte order. The PowerPC architecture
does not use this term.
MS. . . . . . . . . . . . . . . . . . . . . Motorola Scalable
msb . . . . . . . . . . . . . . . . . . . . most significant bit—highest-order bit in an address, register, data element, or instruction encoding.
MSB . . . . . . . . . . . . . . . . . . . Most Significant Byte—highest-order Byte in an address, register, data element, or instruction encoding.
MSCAN . . . . . . . . . . . . . . . . Motorola Scalable CAN (Controller Area Network)
MSR . . . . . . . . . . . . . . . . . . . Main Shift Register, or Machine State Register
N
NaN. . . . . . . . . . . . . . . . . . . . Not a Number
NCITS. . . . . . . . . . . . . . . . . . Number of Cells In Time Slot
NIC . . . . . . . . . . . . . . . . . . . . Network Interface Card
NMI. . . . . . . . . . . . . . . . . . . . Non-Maskable Interrupt
NMSI . . . . . . . . . . . . . . . . . . Non-Multiplexed Serial Interface
No-op . . . . . . . . . . . . . . . . . . No-operation—a single-cycle operation that does not affect registers or generate bus activity
NRT. . . . . . . . . . . . . . . . . . . . Non-Real Time