Freescale Semiconductor MPC5200B - Manual (Page 748)

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MPC5200B Users Guide, Rev. 1
Freescale Semiconductor A-9
PTE . . . . . . . . . . . . . . . . . . . . Page Table Entry
PTI. . . . . . . . . . . . . . . . . . . . . Payload Type Identifier
PTP . . . . . . . . . . . . . . . . . . . . Port-To-Port switching
PTR . . . . . . . . . . . . . . . . . . . . Program Trace
PVR. . . . . . . . . . . . . . . . . . . . Processor Version Register
PWM. . . . . . . . . . . . . . . . . . . Pulse Width Modulator
Q
QNX . . . . . . . . . . . . . . . . . . . From QNX Software Systems—a hybrid realtime platform that represents a cross between a realtime operating
system and a platform OS. The first integrated, self-hosted, graphical platform for embedded developers.
Quad word. . . . . . . . . . . . . . . A group of 16 contiguous locations starting at an address divisible by 16.
R
rA . . . . . . . . . . . . . . . . . . . . . The rA instruction field specifies a GPR used as a source or destination.
rB . . . . . . . . . . . . . . . . . . . . . The rB instruction field specifies a GPR used as a source.
rD . . . . . . . . . . . . . . . . . . . . . The rD instruction field specifies a GPR used as a destination.
rS. . . . . . . . . . . . . . . . . . . . . . The rS instruction field specifies a GPR used as a source.
RCT. . . . . . . . . . . . . . . . . . . . Receive Connection Table
RD. . . . . . . . . . . . . . . . . . . . . Read
Real address mode . . . . . . . . An MMU mode when no address translation is done and the effective address specified is the same as the
physical address. The processor’s MMU is operating in real address mode if its ability to perform address
translation has been disabled through the MSR registers IR and/or DR bits.
Record bit . . . . . . . . . . . . . . . Bit 31 (or the Rc bit) in the instruction encoding. When set, it updates the condition register (CR) to reflect the
result of the operation.
Registers . . . . . . . . . . . . . . . . See Section XXX
Register indirect addressing. . A form of addressing that specifies one GPR that contains the address for the load or store.
Register indirect with . . . . . . A form of addressing that specifies an immediate value to
immediate index addressing. . be added to the contents of a specified GPR to form the target address for the load or store.
Register indirect with . . . . . . A form of addressing that specifies that the contents of two
index addressing . . . . . . . . . . GPRs be added together to yield the target address for the load or store.
Reservation . . . . . . . . . . . . . . The processor establishes a reservation on a cache block of memory space when it executes an lwarx instruction
to read a memory semaphore into a GPR.
Reserved field . . . . . . . . . . . . In a register, a reserved field is one not assigned a function. A reserved field may be a single bit. The handling
of reserved bits is implementation-dependent. Software is allowed to write any value to such a bit. A subsequent
reading of the bit returns 0 if the value last written to the bit was 0; otherwise, it returns an undefined value (0
or 1).
RISC . . . . . . . . . . . . . . . . . . . Reduced Instruction Set Computing—an architecture characterized by fixed-length instructions with
non-overlapping functionality and a separate set of load and store instructions that perform memory access.
RM . . . . . . . . . . . . . . . . . . . . Resource Management
rst . . . . . . . . . . . . . . . . . . . . . reset
RSV. . . . . . . . . . . . . . . . . . . . Reservation
RT . . . . . . . . . . . . . . . . . . . . . Real Time
RTC. . . . . . . . . . . . . . . . . . . . Real-Time Clock
RTOS. . . . . . . . . . . . . . . . . . . Real-Time Operating System
R/W . . . . . . . . . . . . . . . . . . . Read/Write
rwc . . . . . . . . . . . . . . . . . . . . read-write-clear
RWITM. . . . . . . . . . . . . . . . . Read With Intent To Modify
Rx, RX . . . . . . . . . . . . . . . . . Receive
S
SAR. . . . . . . . . . . . . . . . . . . . Segment And Reassemble