3 status register (0x04) - sr, Status register (0x04) — sr -7, Stop-bit lengths -7 – Freescale Semiconductor MPC5200B User Manual
Page 519: Status register (0x04) — sr, 3 status register (0x04)
MPC5200B Users Guide, Rev. 1
15-8
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.3
Status Register (0x04)
—
SR
The read-only SR register shows status of the transmitter, the receiver, and the FIFO.
3
TxCTS
UART / SIR—Transmitter clear-to-send—If both TxCTS and TxRTS are enabled, TxCTS controls the
operation of the transmitter. TxCTS is not used in Codec mode.
0 =
CTS has no effect on the transmitter.
1 = Enables clear-to-send operation. The transmitter checks the state of
CTS each time it is ready
to send a character.
If
CTS is asserted, the character is sent
If it is negated, the channel TxD remains in a high state and transmission is delayed until
CTS is
asserted.
Changes in
CTS as a character is being sent do not affect its transmission.
other Modes—Reserved
4:7
SB
UART—Stop-Bit (length control)—Selects the stop bit length that is appended to the transmitted
character. Stop-bit lengths of 9/16th to 2 bits are programmable for 6-, 8-bit characters. Lengths of 1
1/16th to 2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high
condition at the center of the first stop-bit position, that is, one bit-time after the last data bit or after
the parity bit, if parity is enabled. Therefore the receiver doesn’t support a stop bit length less than
one. Not used in Codec mode, see
other Modes—Reserved
Table 15-9. Stop-Bit Lengths
SB
5 Bits
6–8 Bits
SB
5 Bits
6–8 Bits
SB
5–8 Bits
SB
5–8 Bits
0000
1.063
0.563
0100
1.313
0.813
1000
1.563
1100
1.813
0001
1.125
0.625
0101
1.375
0.875
1001
1.625
1101
1.875
0010
1.188
0.688
0110
1.438
0.938
1010
1.688
1110
1.938
0011
1.250
0.750
0111
1.500
1.000
1011
1.750
1111
2.000
Table 15-10. Status Register (0x04) for UART Mode
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
RB
FE
PE
ORERR
Tx
EMP
Tx
RD
Y
FF
ULL
Rx
RD
Y
CDE
Error
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 15-11. Status Register (0x04) for SIR Mode
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
RB
FE
PE
ORERR
Tx
EMP
Tx
R
D
Y
FF
U
L
L
RxRD
Y
Re
s
e
rv
e
d
Error
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description