Freescale Semiconductor MPC5200B - Manual (Page 165)

MPC5200B Users Guide, Rev. 1
7-6 Freescale Semiconductor
Interrupt Controller
Bits Name Description
— Per_mask Bits 0:23—To mask/accept individual peripheral interrupt sources. This masking is in
addition to interrupt enables, which may exist in each source module.
0=Accept interrupt from source module.
1=Ignore interrupt from source module.
Important —See Note 1 .
0 Per_mask BestComm interrupt source
1 Per_mask Peripheral 1 (PSC1)
2 Per_mask Peripheral 2 (PSC2)
3 Per_mask Peripheral 3 (PSC3)
4 Per_mask Peripheral 4 (PSC6)
5 Per_mask Peripheral 5 (Ethernet)
6 Per_mask Peripheral 6 (USB)
7 Per_mask Peripheral 7 (ATA)
8 Per_mask Peripheral 8 (PCI Control module)
9 Per_mask Peripheral 9 (PCI SC Initiator RX)
10 Per_mask Peripheral 10 (PCI SC Initiator TX)
11 Per_mask Peripheral 11 (PSC4)
12 Per_mask Peripheral 12 (PSC5)
13 Per_mask Peripheral 13 (SPI modf)
14 Per_mask Peripheral 14 (SPI spif)
15 Per_mask Peripheral 15 (I2C1)
16 Per_mask Peripheral 16 (I2C2)
17 Per_mask Peripheral 17 (CAN1)
18 Per_mask Peripheral 18 (CAN2)
19 Per_mask Reserved
20 Per_mask Reserved
21 Per_mask Peripheral 21 (XLB Arbiter)
22 Per_mask Peripheral 22 (BDLC)
23 Per_mask Peripheral 23 (BestComm LocalPlus)
24:31 — Reserved
Note:
1. Setting these bits prevents an interrupt being presented to the e300 core pins for the masked sources. Encoded status
indications in the ICTL Perstat, MainStat, CritiStat Encoded Register are suppressed, but the binary "all" status bits (PSa
in ICTL Peripheral Interrupt Status All Register) are active as long as the source module is presenting an active input to
the Interrupt Controller.