Freescale Semiconductor MPC5200B - Manual (Page 180)

Interrupt Controller
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 7-21
7.2.4.16 ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548
27 PEa17 CAN1
28 PEa18 CAN2
29:30 — Reserved
31 PEa21 XLB Arbiter
Table 7-19. ICTL IRQ Interrupt Emulation All Register
msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R Reserved IRQEa Reserved
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R Reserved
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
0:3 — Reserved
— IRQEa[x] This register provides a way for software to emulate the assertion of a particular external
interrupt pin. The actual interrupt is the OR of the normal interrupt source and each of these
IRQEa[x] bits.
This register represents the four IRQ inputs. This register is redundant with IICTL Main
Interrupt Emulation All Register for IRQ1-3 but is the only source to emulate IRQ0. It provides
a single register with which to test and develop an ISR for the external interrupt sources.
Each bit operates as if it were the pin itself, i.e. edge sensitive operation would require
multiple test writes to create the emulation of a pulsing input. See Note
1
4 IRQEa0 IRQ[0] input pin emulation
5 IRQEa1 IRQ[1] input pin emulation
6 IRQEa2 IRQ[2] input pin emulation
7 IRQEa3 IRQ[3] input pin emulation
8:31 — Reserved
Note:
1. The emulation is only possible if the IRQ pins are externally pulled down. Otherwise the OR between the external pin
values and the IRQEa[x] bits is whole the time one.
Bits Name Description