4 configuration register 2-mbar + 0x010c – Freescale Semiconductor MPC5200B User Manual
Page 260
Memory Controller Registers (MBAR+0x0100:0x010C)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
8-27
8.7.4
Configuration Register 2—MBAR + 0x010C
The 32-bit read/write Configuration register 2 stores delay values necessary between specific SDRAM commands. During initialization,
software loads values to the register according to the SDRAM information obtained from the data sheet. This register is reset only by a
power-up reset signal.
The Burst Length field must be exact. All other fields govern the relative timing from one command to another, they have minimum values
but any larger value is also legal (but with decreased performance).
All delays in this register are expressed in MEM_CLK.
16
—
Reserved
17:19
pre2act
Precharge to Active or Refresh delay.
Suggested value at 132 MHz = 0x02
Rule: t
RP
/MEM_CLK-1. Round up to nearest integer.
EXAMPLE:
If t
RP
= 20ns and MEM_CLK = 99 MHz
20ns / 10.1 ns = 1.98; round to 2; write 0x1.
If t
RP
= 20 ns and MEM_CLK = 132 MHz
20ns / 7.5 ns = 2.66; round to 3; write 0x2.
20:23
ref2act
Refresh to Active delay.
Suggested value at 132 MHz = 0x9
Rule: t
RFC
/MEM_CLK - 1. Round up to nearest integer.
EXAMPLE:
If t
RFC
= 75ns and MEM_CLK = 99 MHz
75ns / 10.1ns = 7.425; round to 8; write 0x7.
If t
RFC
= 75ns and MEM_CLK = 132 MHz
75ns / 7.5ns = 10; round to 9; write 0x9.
24
—
Reserved
25:27
wr_latency
Write latency.
For DDR, write 0x3
For SDR, write 0x0
28:31
—
Reserved
Table 8-11. Memory Controller Configuration Register 2
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
brd2rp
bwt2rwp
brd2wt
burst_length
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description