6 sdma interrupt pending register-mbar + 0x1214, Section 13-6, sdma interrupt pending register – Freescale Semiconductor MPC5200B User Manual
Page 440
BestComm DMA Registers—MBAR+0x1200
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
13-7
13.15.6
SDMA Interrupt Pending Register—MBAR + 0x1214
Bit
Name
Description
0:7
IntVect1
The Interrupt Vector register is used during interrupt acknowledge read cycles. The high
order four bits are programmed by the user, and the low order four bits are decoded from
either the current task number or execution unit. If any task interrupts are asserted,
Interrupt Vector 1 is driven during the interrupt acknowledge cycle. If the task interrupts are
negated and the execution unit interrupts are asserted, Interrupt Vector 2 is driven during
the interrupt acknowledge cycle. The registers are set to the uninitialized vector $0F by
system reset.
The interrupt A number is prioritized with IPR[15] the highest and IPR[0] the lowest. If all
interrupt mask bits are set, then INA[3:0] = 1111 is read from this location.
The interrupt B number is prioritized with the dbgInterrupt as the highest and euInterrupt[0]
the lowest. If all interrupt mask bits are set, then INB[3:0] = 1111 is read from this location.
8:15
IntVect2
See above
16
T/I
T/I: Task/Iniator priority. Set to ‘1’ to switch to “TASK priority” control; set to ‘0’ to revert to
INITIATOR (Requestor) Priority mode.
The priority level of either the TASK or the initiator is set in the register IPR0 through IPR31
17
TEA
TEA: If set to ‘1’ a TEA received by BestComm will be ignored and the task will NOT be
halted. TEA indication can still trigger an interrupt if the proper mask bit is cleared in the
Interrupt Mask Register and the TEA status bit plus the TASK number of the task which
received the TEA are still updated in the Interrupt Pending Register.
18
HE
HE = 1; allows smartDMA higher task number same request priority to block current task,
and allow arbitration.
HE = 0; disables higher task number from blocking. This bit is cleared by reset.
19:30
—
Reserved
31
PE
Prefetch Disable: set to ‘1’ to disable prefetch. Set to ‘0’ to enable prefetch on CommBus
Table 13-6. SDMA Interrupt Pending Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
DBG
Rsvd
TEA
Etn[3:0]
EU[7:0]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
TASK[15:0]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0