Freescale Semiconductor MPC5200B - Manual (Page 176)

Interrupt Controller
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 7-17
7.2.4.12 ICTL Peripheral Interrupt Status All Register—MBAR + 0x0530
23 MSa8 GPIO WakeUp interrupt
24 MSa9 TMR0 interrupt
25 MSa10 TMR1 interrupt
26 MSa11 TMR2 interrupt
27 MSa12 TMR3 interrupt
28 MSa13 TMR4 interrupt
29 MSa14 TMR5 interrupt
30 MSa15 TMR6 interrupt
31 MSa16 TMR7 interrupt
Note:
1. All main interrupt sources are directly maskable in Main_Mask, ICTL Critical Priority and Main Interrupt Mask Register.
If masked in Main_Mask, status information still shows in MSa. However, if interrupt is not enabled at the source module
(i.e., in source module registers) the Interrupt Controller cannot observe or record status information for that interrupt.
Table 7-15. ICTL Peripheral Interrupt Status All Register
msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R Reserved PSa
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R PSa Reserved PSa21
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
0:7 — Reserved
— PSa[x] Peripheral Interrupt Status All. Indicates all pending interrupts. Is binary, showing each active
interrupt in its corresponding bit position. See Note
1 .
Number in parenthesis indicates equivalent encoded value in PSe, ICTL PerStat, MainStat,
CritStat Encoded Register.
8 PSa23 BestComm LocalPlus
9 PSa22 BDLC
10 PSa0 BestComm interrupt source
11 PSa1 PSC1
12 PSa2 PSC2
13 PSa3 PSC3
14 PSa4 PSC6
15 PSa5 Ethernet
Bits Name Description