Gpw wakeup gpio interrupt types register – Freescale Semiconductor MPC5200B User Manual
Page 210
General Purpose I/O (GPIO)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
7-51
7.3.2.2.7
GPW WakeUp GPIO Interrupt Types Register—MBAR + 0x0C18
Bit
Name
Description
0:7
WINe
Individual bits to enable generation of Simple interrupt for WakeUp GPIO configured as
input.
Bit 0 controls GPIO_WKUP_7 (GPIO_WKUP_7 pin)
Bit 1 controls GPIO_WKUP_6 (GPIO_WKUP_6 pin)
Bit 2 controls GPIO_WKUP_5 (PSC6_1 pin)
Bit 3 controls GPIO_WKUP_4 (PSC6_0 pin)
Bit 4 controls GPIO_WKUP_3 (ETH_17 pin)
Bit 5 controls GPIO_WKUP_2 (PSC3_9 pin)
Bit 6 controls GPIO_WKUP_1 (PSC2_4 pin)
Bit 7 controls GPIO_WKUP_0 (PSC1_4 pin)
0 = Pin cannot generate Simple Interrupt (default).
1 = Pin can generate Simple Interrupt while MPC5200B is not in Deep Sleep mode.
Note: These enable bits apply only when MPC5200B is not in Deep Sleep mode.
8:31
—
Reserved
Note: Only valid when Port Configuration indicates GPIO usage and pin is configured as input in the associated DDR
bit in GPIOWDO. Also, Master Interrupt Enable bit in GPIOWME must be set.
Table 7-43. GPW WakeUp GPIO Interrupt Types Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Ityp7
Ityp6
Ityp5
Ityp4
Ityp3
Ityp2
Ityp7
Ityp0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0