Freescale Semiconductor MPC5200B - Manual (Page 187)

MPC5200B Users Guide, Rev. 1
7-28 Freescale Semiconductor
General Purpose I/O (GPIO)
• Timer pins 6 and 7 are dedicated as Timer GPIO and have no alternate function.
Although the Timer as GPIO only operates to the Simple GPIO level, Interrupt capability can be achieved by configuring the Timer for Input
Capture mode.
7.3.1.9 Dedicated GPIO Port
There is a dedicated GPIO port group that consists of 2 pins. Both pins operate at the WakeUp GPIO level. They are designated:
• GPIO_WKUP_6
• GPIO_WKUP_7
However, GPIO_WKUP_6 is not dedicated and can be programmed to operate as a second SDRAM memory chip select. As such, this pin is
connected to the Memory Vdd supply. For Dual Data Rate memory, the GPIO_WKUP_6 pin is driven at the reduced 2.5V level.
If not used as a memory chip select, the GPIO_WKUP_6 pin serves as a memory voltage compatible GPIO.
7.3.2 GPIO Programmer’s Model
The GPIO programmer’s model contains 3 separate register sets (or modules), each at different offsets from MBAR. These register sets are:
1. GPIO Standard Registers—MBAR+0x0B00 . Output Only, Simple, and Interrupt GPIO are controlled by registers within this
module. There are 3 register groupings for individual control of each of the named GPIO types.
2. WakeUp GPIO Registers—MBAR+0x0C00 . WakeUp GPIO are controlled by this register set
3. GPT Registers—MBAR + 0x0600 . Timer functions and Timer GPIO are controlled by this module.
All GPIO functionality is dependent on the Port Configuration Register (PCR) setting. The PCR is the first register in the GPIO Standard
Module. This register controls the Pin MUX Logic. Therefore, the PCR also controls the physical routing of MPC5200B I/O pins to and from
internal logic. The PCR is expected to be configured early in the boot process and set to a static value that supports the given peripheral set
of a specific application.
NOTE
The PCR is not accessible during Deep Sleep mode.
7.3.2.1 GPIO Standard Registers—MBAR+0x0B00
The GPIO Standard Register set has separate registers for each GPIO type.
• Simple
• Output Only
• Interrupt
These registers are at an offset of MBAR + 0x0B00.
The GPIO Standard Register set uses 16 32-bit registers. These registers are located at an offset from MBAR of 0x0B00. Register addresses
are relative to this offset. Therefore, the actual register address is:
MBAR + 0x0B00 + register address
Hyperlinks to the GPIO pin type registers are provided below:
• GPS Port Configuration Register (0x0B00) • GPS GPIO Simple Interrupt Enables Register (0x0B20)
• GPS Simple GPIO Enables Register (0x0B04) • GPS GPIO Simple Interrupt Open-Drain Emulation
Register
(0x0B24)
• GPS Simple GPIO Open Drain Type Register (0x0B08) • GPS GPIO Simple Interrupt Data Direction Register
(0x0B28)
• GPS Simple GPIO Data Direction Register (0x0B0C) • GPS GPIO Simple Interrupt Data Value Out Register
(0x0B2C)
• GPS Simple GPIO Data Output Values Register
(0x0B10)
• GPS GPIO Simple Interrupt Interrupt Enable Register
(0x0B30)
• GPS Simple GPIO Data Input Values Register
(0x0B14)
• GPS GPIO Simple Interrupt Interrupt Types Register
(0x0B34)
• GPS GPIO Output-Only Enables Register (0x0B18) • GPS GPIO Simple Interrupt Master Enable Register
(0x0B38)
• GPS GPIO Output-Only Data Value Out Register
(0x0B1C)
• GPS GPIO Simple Interrupt Status Register (0x0B3C)