Freescale Semiconductor 56F8122 User Manual
Freescale Semiconductor Hardware
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Table of contents
Document Outline
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- Part 3 On-Chip Clock Synthesis (OCCS)
- Part 4 Memory Map
- Part 5 Interrupt Controller (ITCN)
- 5.1 Introduction
- 5.2 Features
- 5.3 Functional Description
- 5.4 Block Diagram
- 5.5 Operating Modes
- 5.6 Register Descriptions
- 5.6.1 Interrupt Priority Register 0 (IPR0)
- 5.6.2 Interrupt Priority Register 1 (IPR1)
- 5.6.3 Interrupt Priority Register 2 (IPR2)
- 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level (FMCBE IPL)—Bi...
- 5.6.3.2 Flash Memory Command Complete Priority Level (FMCC IPL)—Bits 13–12
- 5.6.3.3 Flash Memory Error Interrupt Priority Level (FMERR IPL)—Bits 11–10
- 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8
- 5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 7–6
- 5.6.3.6 Reserved—Bits 5–2
- 5.6.3.7 External IRQ A Interrupt Priority Level (IRQA IPL)—Bits 1–0
- 5.6.4 Interrupt Priority Register 3 (IPR3)
- 5.6.4.1 Reserved—Bits 15–10
- 5.6.4.2 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—Bits 9–8
- 5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)— Bits 7–6
- 5.6.4.4 FlexCAN Error Interrupt Priority Level (FCERR IPL)— Bits 5–4
- 5.6.4.5 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2
- 5.6.4.6 Reserved—Bits 1–0
- 5.6.5 Interrupt Priority Register 4 (IPR4)
- 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14
- 5.6.5.2 SPI1 Transmit Empty Interrupt Priority Level (SPI1_XMIT IPL)— Bits 13–12
- 5.6.5.3 SPI1 Receiver Full Interrupt Priority Level (SPI1_RCV IPL)— Bits 11–10
- 5.6.5.4 Reserved—Bits 9–6
- 5.6.5.5 GPIO_A Interrupt Priority Level (GPIOA IPL)—Bits 5–4
- 5.6.5.6 GPIO_B Interrupt Priority Level (GPIOB IPL)—Bits 3–2
- 5.6.5.7 GPIO_C Interrupt Priority Level (GPIOC IPL)—Bits 1–0
- 5.6.6 Interrupt Priority Register 5 (IPR5)
- 5.6.6.1 Reserved—Bits 15–12
- 5.6.6.2 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10
- 5.6.6.3 SCI1 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)— Bits 9–8
- 5.6.6.4 Reserved—Bits 7–6
- 5.6.6.5 SCI1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4
- 5.6.6.6 SCI1 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL)— Bits 3–2
- 5.6.6.7 SPI0 Transmitter Empty Interrupt Priority Level (SPI0_XMIT IPL)— Bits 1–0
- 5.6.7 Interrupt Priority Register 6 (IPR6)
- 5.6.8 Interrupt Priority Register 7 (IPR7)
- 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14
- 5.6.8.2 Reserved—Bits 13–6
- 5.6.8.3 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4
- 5.6.8.4 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2
- 5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)—Bits 1–0
- 5.6.9 Interrupt Priority Register 8 (IPR8)
- 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)— Bits 15–14
- 5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL)— Bits 13–12
- 5.6.9.3 Reserved—Bits 11–10
- 5.6.9.4 SCI0 Transmitter Idle Interrupt Priority Level (SCI0_TIDL IPL)— Bits 9–8
- 5.6.9.5 SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6
- 5.6.9.6 Timer A, Channel 3 Interrupt Priority Level (TMRA3 IPL)—Bits 5–4
- 5.6.9.7 Timer A, Channel 2 Interrupt Priority Level (TMRA2 IPL)—Bits 3–2
- 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)—Bits 1–0
- 5.6.10 Interrupt Priority Register 9 (IPR9)
- 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMAF IPL)—Bits 15–14
- 5.6.10.2 Reserved—Bits 13–12
- 5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL)— Bits 11–10
- 5.6.10.4 Reserved—Bits 9–8
- 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level (ADCA_ZC IPL)—Bits 7–6
- 5.6.10.6 Reserved—Bits 5–4
- 5.6.10.7 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)—Bits 3–2
- 5.6.10.8 Reserved—Bits 1–0
- 5.6.11 Vector Base Address Register (VBA)
- 5.6.12 Fast Interrupt 0 Match Register (FIM0)
- 5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
- 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)
- 5.6.15 Fast Interrupt 1 Match Register (FIM1)
- 5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
- 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)
- 5.6.18 IRQ Pending 0 Register (IRQP0)
- 5.6.19 IRQ Pending 1 Register (IRQP1)
- 5.6.20 IRQ Pending 2 Register (IRQP2)
- 5.6.21 IRQ Pending 3 Register (IRQP3)
- 5.6.22 IRQ Pending 4 Register (IRQP4)
- 5.6.23 IRQ Pending 5 Register (IRQP5)
- 5.6.24 Reserved—Base + 17
- 5.6.25 Reserved—Base + 18
- 5.6.26 Reserved—Base + 19
- 5.6.27 Reserved—Base + 1A
- 5.6.28 Reserved—Base + 1B
- 5.6.29 Reserved—Base + 1C
- 5.6.30 ITCN Control Register (ICTL)
- 5.6.30.1 Interrupt (INT)—Bit 15
- 5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13
- 5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
- 5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5
- 5.6.30.5 Reserved—Bit 4
- 5.6.30.6 Reserved—Bit 3
- 5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
- 5.6.30.8 Reserved—Bit 1
- 5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0
- 5.7 Resets
- Part 6 System Integration Module (SIM)
- 6.1 Introduction
- 6.2 Features
- 6.3 Operating Modes
- 6.4 Operating Mode Register
- 6.5 Register Descriptions
- 6.5.1 SIM Control Register (SIM_CONTROL)
- 6.5.2 SIM Reset Status Register (SIM_RSTSTS)
- 6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3)
- 6.5.4 Most Significant Half of JTAG ID (SIM_MSH_ID)
- 6.5.5 Least Significant Half of JTAG ID (SIM_LSH_ID)
- 6.5.6 SIM Pull-up Disable Register (SIM_PUDR)
- 6.5.7 CLKO Select Register (SIM_CLKOSR)
- 6.5.8 SIM GPIO Peripheral Select Register (SIM_GPS)
- 6.5.9 Peripheral Clock Enable Register (SIM_PCE)
- 6.5.9.1 Reserved—Bits 15–14
- 6.5.9.2 Analog-to-Digital Converter A Enable (ADCA)—Bit 13
- 6.5.9.3 FlexCAN Enable (CAN)—Bit 12
- 6.5.9.4 Reserved—Bit 11
- 6.5.9.5 Decoder 0 Enable (DEC0)—Bit 10
- 6.5.9.6 Reserved—Bit 9
- 6.5.9.7 Quad Timer C Enable (TMRC)—Bit 8
- 6.5.9.8 Reserved—Bit 7
- 6.5.9.9 Quad Timer A Enable (TMRA)—Bit 6
- 6.5.9.10 Serial Communications Interface 1 Enable (SCI1)—Bit 5
- 6.5.9.11 Serial Communications Interface 0 Enable (SCI0)—Bit 4
- 6.5.9.12 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3
- 6.5.9.13 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2
- 6.5.9.14 Reserved—Bit 1
- 6.5.9.15 Pulse Width Modulator A Enable (PWMA)—Bit 0
- 6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
- 6.6 Clock Generation Overview
- 6.7 Power-Down Modes
- 6.8 Stop and Wait Mode Disable Function
- 6.9 Resets
- Part 7 Security Features
- Part 8 General Purpose Input/Output (GPIO)
- Part 9 Joint Test Action Group (JTAG)
- Part 10 Specifications
- 10.1 General Characteristics
- 10.2 DC Electrical Characteristics
- 10.3 AC Electrical Characteristics
- 10.4 Flash Memory Characteristics
- 10.5 External Clock Operation Timing
- 10.6 Phase Locked Loop Timing
- 10.7 Oscillator Parameters
- 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 10.9 Serial Peripheral Interface (SPI) Timing
- 10.10 Quad Timer Timing
- 10.11 Quadrature Decoder Timing
- 10.12 Serial Communication Interface (SCI) Timing
- 10.13 Controller Area Network (CAN) Timing
- 10.14 JTAG Timing
- 10.15 Analog-to-Digital Converter (ADC) Parameters
- 10.16 Equivalent Circuit for ADC Inputs
- 10.17 Power Consumption
- Part 11 Packaging
- Part 12 Design Considerations
- Part 13 Ordering Information