2 interrupt priority level (ipic)—bits 14–13, 4 interrupt disable (int_dis)—bit 5, 5 reserved—bit 4 – Freescale Semiconductor 56F8122 User Manual
Page 76: 6 reserved—bit 3, 7 irqa state pin (irqa state)—bit 2, 8 reserved—bit 1, 9 irqa edge pin (irqa edg)—bit 0
56F8322 Techncial Data, Rev. 10.0
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Freescale Semiconductor
Preliminary
5.6.30.2 Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
•
00 = Required nested exception priority levels are 0, 1, 2, or 3
•
01 = Required nested exception priority levels are 1, 2, or 3
•
10 = Required nested exception priority levels are 2 or 3
•
11 = Required nested exception priority level is 3
5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.6.30.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
0 = Normal operation (default)
•
1 = All interrupts disabled
5.6.30.5 Reserved—Bit 4
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6 Reserved—Bit 3
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.7 IRQA State Pin (IRQA STATE)—Bit 2
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8 Reserved—Bit 1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.9 IRQA Edge Pin (IRQA Edg)—Bit 0
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
•
0 = IRQA interrupt is a low-level sensitive (default)
•
1 = IRQA interrupt is falling-edge sensitive