Ted in, Figure 2-1 – Freescale Semiconductor 56F8122 User Manual
Page 15
Introduction
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
15
Preliminary
Figure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQFP)
V
DD_IO
V
DDA_ADC
V
SSA_ADC
EXTAL (GPIOC0)
XTAL (GPIOC1)
Other
Supply
Ports
PLL and
Clock or
GPIO
JTAG/
EOnCE
Port
4
1
4
V
CAP
1 - V
CAP
2
2
1
1
TCK
TMS
Quadrature
Decoder 0
or Quad
Timer A or
GPIO
PHASEA0 (TA0, GPIOB7)
PWMA3 (MISO1, GPIOA3)
ANA0 - 2
IRQA (V
PP
)
RESET
SPI0 or
SCI1 or
GPIO
PWMA or
SPI1 or
GPIO
Quad Timer C
or SCI0 or
GPIO
1
1
1
1
3
3
1
1
1
56F8322
1
TDI
TDO
PHASEB0 (TA1, GPIOB6)
INDEX0 (TA2, GPIOB5)
HOME0 (TA3, GPIOB4)
SCLK0 (GPIOB3)
MOSI0 (GPIOB2)
MISO0 (RXD1, GPIOB1)
SS0 (TXD1, GPIOB0)
CAN_RX (GPIOC2)
CAN_TX (GPIOC3)
TC0 (TXD0, GPIOC6)
ADCA
FlexCAN
or GPIO
Interrupt/
Program
Control
1
1
1
1
1
1
1
1
1
1
1
1
1
V
REF
ANA4 - 6
3
V
SS
Power
Ground
Power
Ground
PWMA2 (SS1, GPIOA2)
1
PWMA0 -1 (GPIOA0 - 1)
2
PWMA4 (MOSI1, GPIOA4)
1
PWMA5 (SCLK1, GPIOA5)
1
FAULTA0 (GPIOA6)
1
TC1 (RXD0, GPIOC5)
Note: V
REFH
is tied to V
DDA
and V
REFLO
is tied to V
SSA
inside this package