Freescale Semiconductor 56F8122 - Manual (Page 19)

Signal Pins
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 19
Preliminary
PHASEA0
(TA0)
(GPIOB7)
(oscillator_
clock)
38 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
Input
Input
Input
Output
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal oscillator clock
signal (see
Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEA0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
PHASEB0
(TA1)
(GPIOB6)
(SYS_CLK2)
37 Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Output
Input
Input
Input
Output
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A ,Channel 1
Port B GPIO — This GPIO pin can be individually programmed as an
input or output pin.
Clock Output - can be used to monitor the internal SYS_CLK2 signal
(see
Section 6.5.7 CLKO Select Register, SIM_CLKOSR).
In the 56F8322, the default state after reset is PHASEB0.
In the 56F8122, the default state is not one of the functions offered
and must be reconfigured.
Table 2-2 Signal and Package Information for the 48-Pin LQFP
Signal Name Pin No. Type
State During
Reset
Signal Description