16 equivalent circuit for adc inputs, 17 power consumption – Freescale Semiconductor 56F8122 User Manual

Page 125

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Equivalent Circuit for ADC Inputs

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

125

Preliminary

10.16 Equivalent Circuit for ADC Inputs

Figure 10-21

illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed

at the same time that S3 is closed/open. When S1/S2 closed & S3 open, one input of the sample and hold
circuit moves to (V

REFH

-V

REFLO

)/2, while the other charges to the analog input voltage. When the

switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V

REFH

-V

REFLO

)/2. The switches switch

on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.

One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V

REF

and the ADC clock frequency.

1.

Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf

2.

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf

3.

Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms

4.

Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1pf

Figure 10-21 Equivalent Circuit for A/D Loading

10.17 Power Consumption

See

Section 10.1

for a list of IDD requirements for the device. This section provides additional detail

which can be used to optimize power consumption for a given application.

Power consumption is given by the following equation:

A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,
PLL, and voltage references. These sources operate independently of processor state or operating
frequency.

Total power =

A: internal [static component]

+B: internal [state-dependent component]
+C: internal [dynamic component]

+D: external [dynamic component]

+E: external [static]

1

2

3

Analog Input

4

S1

S2

S3

C1

C2

S/H

C1 = C2 = 1pF

(V

REFH

- V

REFLO )

/ 2

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