6 reserved—bits 1–0, 5 interrupt priority register 4 (ipr4), Figure 5-7 interrupt priority register 4 (ipr4) – Freescale Semiconductor 56F8122 User Manual
Page 61
Register Descriptions
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
61
Preliminary
5.6.4.3
FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL)—
Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
5.6.4.4
FlexCAN Error Interrupt Priority Level (FCERR IPL)—
Bits 5–4
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
5.6.4.5
FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
5.6.4.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.5
Interrupt Priority Register 4 (IPR4)
Figure 5-7 Interrupt Priority Register 4 (IPR4)
Base + $4
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
SPI0_RCV
IPL
SPI1_XMIT
IPL
SPI1_RCV
IPL
0
0
0
0
GPIOA IPL
GPIOB IPL
GPIOC IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0