Freescale Semiconductor 56F8122 - Manual (Page 113)

Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 113
Preliminary
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note: All address and data buses described here are internal.
Figure 10-5 Asynchronous Reset Timing
Figure 10-6 External Interrupt Timing (Negative Edge-Sensitive)
Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1. In the formulas, T = clock cycle. For an operating frequency of 60MHz, T = 16.67ns. At 8MHz (used during Reset and Stop
modes), T = 125ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol
Typical
Min
Typical
Max
Unit
See
Figure
Minimum RESET Assertion Duration t
RA
16T — ns 10-5
Edge-sensitive Interrupt Request Width t
IRW
1.5T — ns 10-6
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine t
IG
18T — ns 10-7
t
IG - FAST
14T —
IRQA Width Assertion to Recover from Stop State 3
3. The interrupt instruction fetch is visible on the pins only in Mode 3.
t
IW
1.5T — ns 10-8
First Fetch
t
RA
t
RAZ
t
RDA
PAB
PDB
RESET
IRQA
t
IRW