Freescale Semiconductor 56F8122 - Manual (Page 53)

Functional Description
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 53
Preliminary
5.3.2 Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
5.3.3 Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
fast interrupts before the core does.
A fast interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the fast interrupt
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a fast interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector adddress and if it is not a JSR, the core starts
its fast interrupt handling.
Table 5-1 Interrupt Mask Bit Definition
SR[9]
1
1. Core status register bits indicating current interrupt mask within the core.
SR[8]
1 Permitted Exceptions Masked Exceptions
0 0 Priorities 0, 1, 2, 3 None
0 1 Priorities 1, 2, 3 Priority 0
1 0 Priorities 2, 3 Priorities 0, 1
1 1 Priority 3 Priorities 0, 1, 2
Table 5-2. Interrupt Priority Encoding
IPIC_LEVEL[1:0]
1
1. See IPIC field definition in Section 5.6.30.2
Current Interrupt
Priority Level
Required Nested
Exception Priority
00 No Interrupt or SWILP Priorities 0, 1, 2, 3
01 Priority 0 Priorities 1, 2, 3
10 Priority 1 Priorities 2, 3
11 Priorities 2 or 3 Priority 3