Freescale Semiconductor 56F8122 - Manual (Page 80)

56F8322 Techncial Data, Rev. 10.0
80 Freescale Semiconductor
Preliminary
Figure 6-2 SIM Register Map Summary
6.5.1 SIM Control Register (SIM_CONTROL)
Figure 6-3 SIM Control Register (SIM_CONTROL)
6.5.1.1 Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Add.
Offset
Register
Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
$0
SIM_
CONTROL
R 0 0 0 0 0 0 0 0 0 0 ONCE
EBL 0
SW
RST
STOP_
DISABLE
WAIT_
DISABLE W
$1
SIM_
RSTSTS
R 0 0 0 0 0 0 0 0 0 0
SWR COPR EXTR POR
0 0
W
$2 SIM_SCR0
R
FIELD
W
$3 SIM_SCR1
R
FIELD
W
$4 SIM_SCR2
R
FIELD
W
$5 SIM_SCR3
R
FIELD
W
$6 SIM_MSH_ID
R 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0
W
$7 SIM_LSH_ID
R 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
W
$8 SIM_PUDR
R 0 0 0 0
RESET IRQ
0 0 0 0 0 0
JTAG
0 0 0
W
Reserved
$A
SIM_
CLKOSR
R 0 0 0 0 0 0
PHSA PHSB INDEX HOME
CLK
DIS
CLKOSEL
W
$B SIM_GPS
R 0 0 0 0 0 0 0 0
C6 C5 B1 B0 A5 A4 A3 A2
W
$C SIM_PCE
R 1 1
ADCA CAN
1
DEC0
1
TMRC
1
TMRA SCI1 SCI0 SPI1 SPI0
1
PWMA
W
$D SIM_ISALH
R 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ISAL[23:22]
W
$E SIM_ISALL
R
ISAL[21:6]
W
= Reserved
Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 0 0 0 0 0 0 0 0 0
ONCE
EBL 0
SW
RST
STOP_
DISABLE
WAIT_
DISABLE Write
RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0