Freescale Semiconductor 56F8122 - Manual (Page 133)

Electrical Design Considerations
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 133
Preliminary
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
12.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation of the 56F8322/56F8122:
• Provide a low-impedance path from the board power supply to each V
DD
pin on the device and from the
board ground to each V
SS
(GND) pin
• The minimum bypass requirement is to place six 0.01–0.1
µ
F capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the V
DD
/V
SS
pairs, including V
DDA
/V
SSA.
Ceramic and tantalum capacitors tend to provide better
tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
DD
and V
SS
(GND)
pins are less than 0.5 inch per capacitor lead
• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V
DD
and V
SS
• Bypass the V
DD
and V
SS
layers of the PCB with approximately 100
µ
F, preferably with a high-grade
capacitor such as a tantalum capacitor
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.