4 most significant half of jtag id (sim_msh_id), 5 least significant half of jtag id (sim_lsh_id), 6 sim pull-up disable register (sim_pudr) – Freescale Semiconductor 56F8122 User Manual
Page 83: 1 reserved—bits 15–12, 2 reset—bit 11
Register Descriptions
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
83
Preliminary
6.5.4
Most Significant Half of JTAG ID (SIM_MSH_ID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F4.
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
6.5.5
Least Significant Half of JTAG ID (SIM_LSH_ID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$001D.
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
6.5.6
SIM Pull-up Disable Register (SIM_PUDR)
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see
) corresponds to a functional group of pins. See
to identify which pins can deactivate the internal pull-up resistor.
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
6.5.6.1
Reserved—Bits 15–12
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
RESET—Bit 11
This bit controls the pull-up resistors on the RESET pin.
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
Write
RESET
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
RESET
IRQ
0
0
0
0
0
0
JTAG
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0