3 memory, 4 peripheral circuits – Freescale Semiconductor 56F8122 User Manual
Page 6
56F8322 Techncial Data, Rev. 10.0
6
Freescale Semiconductor
Preliminary
1.1.3
Memory
Note: Features in italics are NOT available in the 56F8122 device.
•
Harvard architecture permits as many as three simultaneous accesses to program and data memory
•
Flash security protection
•
On-chip memory, including a low-cost, high-volume Flash solution
— 32KB of Program Flash
— 4KB of Program RAM
—
8KB
of Data Flash
—
8KB
of Data RAM
—
8KB
of Boot Flash
•
EEPROM emulation capability
1.1.4
Peripheral Circuits
Note: Features in italics are NOT available in the 56F8122 device.
•
One Pulse Width Modulator module with six PWM outputs and one Fault input; fault-tolerant design with
dead time insertion; supports both center-aligned and edge-aligned modes
•
Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with dual,
3-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, Channel 2
•
Temperature Sensor is tied internally to analog input (ANA7) to monitor the on-chip temperature
•
Two 16-bit Quad Timer modules (TMR) totaling six pins:
— In the 56F8322, Timer A works in conjunction with Quad Decoder 0 and Timer C works in conjunction
with the PWMA and ADCA
— In the 56F8122, Timer C works in conjunction with ADCA
•
One Quadature Decoder which works in conjunction with Quad Timer A
•
FlexCAN (Can Version 2.0 B-compliant) module with 2-pin port for transmit and receive
•
Up to
two Serial Communication Interfaces (SCIs)
•
Up to
two Serial Peripheral Interfaces (SPIs)
•
Computer Operating Properly (COP)/Watchdog timer
•
One dedicated external interrupt pin
•
21 General Purpose I/O (GPIO) pins
•
Integrated Power-On Reset and Low-Voltage Interrupt Module
•
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
•
Software-programmable, Phase Lock Loop (PLL)
•
On-chip relaxation oscillator