Freescale Semiconductor MPC5200B - Manual (Page 143)

MPC5200B Users Guide, Rev. 1
5-10 Freescale Semiconductor
Power Management
5.4.3.1 Dynamic Power Mode
This is the default power state mode. The core is fully powered and internal functional units are operating at the full processor clock speed.
If Dynamic Mode is enabled, idle functional units automatically enter a low-power state. This does not effect:
• performance
• software execution
• external hardware
5.4.3.2 Doze Mode
All functional e300 Core units are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is
in Doze Mode, any of the following actions returns the core to Full-Power Mode:
• an external asynchronous interrupt
• a system management interrupt
• a decrementer (DEC) exception
• a hard or soft reset
• a machine check input (MCP) signal
In Doze Mode, the core maintains the PLL in a fully powered state and locked to the system XLB clock input. Transition to Full-Power Mod
takes only a few processor clock cycles.
5.4.3.3 Nap Mode
The Nap Mode further reduces e300 Core power consumption by disabling bus snooping, leaving only the time base register and the PLL in
a powered state. When in Nap Mode, any of the following actions returns the core to Full-Power Mod:
• an external asynchronous interrupt
• a system management interrupt
• a DEC exception
• a hard or soft reset
• an MCP signal
Transition to Full-Power Mode takes only a few processor clock cycles.
NOTE: It is not allowed to set the ccs_sleep_en bit of CDM Clock Control Sequencer Configuration Register before entering the nap mode.
Otherwise all clocks will be disabled by entering the nap mode.
5.4.3.4 Sleep Mode
Sleep Mode reduces e300 Core power consumption to a minimum. It does this by disabling all internal functional units.
Any of the following actions returns the core to Full-Power Mode:
• an external asynchronous interrupt
• a system management interrupt
• a hard or soft reset
• an MCP signal
In Sleep Mode it is possible to disable the e300 Core PLL, further reducing power. this requires special sequencing logic external to the e300
Core and is discussed in
Section 5.4.4, Deep-Sleep Mode .
5.4.4 Deep-Sleep Mode
The MPC5200B system provides a very low power consumption mode where the 27/33MHz system oscillator, system PLL and e300 Core
PLL are shut down and disabled. Once MPC5200B is sequenced into this mode and clocks are static, the current draw of the device (except
the RTC) is reduced to leakage levels. The internal state of the device is maintained in Deep Sleep as long as power is maintained.
The real-time clock (RTC) is not disabled in Deep Sleep. If the RTC is used, that portion of the chip still consumes power in Deep Sleep.
Exiting Deep Sleep mode is initiated in one of the following ways:
• An interrupt from the RTC logic
• An external asynchronous interrupt (wake up interrupt)
• An interrupt from one of the MSCAN modules (which occurs when a data transition occurs on the serial input).
The RTC clock is necessary to wake up MPC5200B using an RTC interrupt. However, no clock is required to trigger the wake up process in
the case of an external interrupt or the MSCAN module interrupt. This means the RTC clock does not have to be present to use Deep Sleep