Freescale Semiconductor MPC5200B - Manual (Page 676)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 19-37
Figure 19-11. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN the INITRQ has to be synchronized to all domains by using a special handshake
mechanism. This handshake causes additional synchronization delay (). If there is no message transfer ongoing on the CAN bus, the minimum
delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in Initialization Mode the INITAK
flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into Initialization Mode.
NOTE
The MCU cannot clear the INITRQ bit before Initialization Mode (INITRQ=1 and INITAK=1) is
active.
19.7.8.6 MSCAN Power Down Mode
The MSCAN is in Power Down Mode when Table 19-35
• the CPU is in Deep Sleep Mode or
• the CPU is in SLEEP Mode and the CSWAI bit is set.
When entering the Power Down Mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN
protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives
the TXCAN pin into a recessive state. In Power-Down modes, no registers can be accessed.
NOTE
The user is responsible for ensuring that the MSCAN is not active when Power Down Mode is
entered. The recommended procedure is to bring the MSCAN into Sleep Mode before the STOP or
WAI instruction (if CSWAI is set) is executed. Otherwise the abort of an ongoing message can cause
an error condition and can have an impact on the other bus devices.
In Power Down Mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in Sleep Mode before Power Down
Mode became active, the module would perform an internal recovery cycle after powering up. This causes some fixed delay before the module
enters Run Mode again.
19.7.8.7 Programmable Wake-Up Function
The MSCAN can be programmed to wake-up the MSCAN as soon as bus activity is detected (see control bit WUPE in Section 19.5.3, MSCAN
Control Register 0 (CANCTL0)—MBAR + 0x0900 / 0x980 ). The sensitivity to existing bus action can be modified by applying a low-pass
filter function to the RXCAN input line while in Sleep Mode (see control bit WUPM in Section 19.5.4, MSCAN Control Register 1
(CANCTL1)—MBAR + 0x0901 / 0x981 ). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus
lines. Such glitches can result, for example, from electromagnetic interference within noisy environments.
19.7.9 Description of Interrupt Operation
The MSCAN supports one interrupt vector mapped onto eight different interrupt sources, any of which can be individually masked (for details
see sections
Section 19.5.8, MSCAN Receiver Interrupt Enable Register (CANRIER)—MBAR + 0x0909 / 0x989 to Section 19.5.10, MSCAN
Transmitter Interrupt Enable Register (CANTIER)—MBAR+0x090D / 0x098D ):
SYNC
SYNC
CPU Clock Domain CAN Clock Domain
CPU
Init Request
INIT
Flag
INITAK
Flag
INITRQ
sync.
INITAK
sync.
INITRQ
INITAK