Freescale Semiconductor MPC5200B - Manual (Page 359)

MPC5200B Users Guide, Rev. 1
10-62 Freescale Semiconductor
PCI Arbiter
10.4.6.8 Alarms
The FIFO alarm registers allow software to control when the DMA fills or empties the appropriate FIFO.
10.4.6.9 Bus Errors
Since Bus Errors are particular to the module register set and that register set includes both Transmit and Receive Controller and FIFO settings,
the Bus Error status bits and Bus error Enable bit(s) are duplicated in the Transmit and Receive register groupings. Clearing or setting one
will clear or set the other. From a software point of view, then, they can be treated separately or together, as desired.
10.4.7 PCI - Supported Clock Ratios
MPC5200B supports the following XL Bus:IP:PCI clock ratios.
10.4.8 Interrupts
10.4.8.1 PCI Bus Interrupts
MPC5200B does not generate interrupts on the PCI bus interrupt lines INTA - INTD.
10.4.8.2 Internal Interrupt
The PCI module is capable of generating 3 interrupts to MPC5200B interrupt controller in MPC5200B SIU. Each interrupt can be enabled
for a variety of conditions, mostly error conditions. For the XL bus Initiator interface, the internal interrupt can be enabled for Retry errors,
Target Aborts and Initiator (Master) Aborts. See
Section 10.3.2.9, Initiator Control Register PCIICR(RW) —MBAR + 0x0D84 and Section
10.3.2.10, Initiator Status Register PCIISR(RWC) —MBAR + 0x0D88 for more information. For the Comm bus Initiator interface, an internal
interrupt can be enabled for FIFO errors and Normal Termination of a packet transfer for either the Receive (rx) or Transmit (tx) interface.
For more information, see the Enable and Status registers for the Comm bus Transmit and Receive interfaces,
Section 10.3.3.1,
Multi-Channel DMA Transmit Interface and Section 10.3.3.2, Multi-Channel DMA Receive Interface .
10.5 PCI Arbiter
The PCI Arbiter is a separate module, it is not part of the PCI Controller module. The 32-bit multiplexed PCI A/D bus is shared with the ATA
Controller and LocalPlus Controller. The on-chip arbiter (called PCI Arbiter) controls the access to the AD bus for the different clients:
• PCI clients
— XIPCI (XL Bus-PCI interface)
— SCPCI (BestComm-PCI interface)
— external PCI
• non-PCI clients
— LPC (LocalPlus bus interface)
— SCLPC (BestComm LocalPlus bus interface)
— ATA
One pair only of external PCI REQ#/GNT# signals is supported by the PCI Arbiter. By an external Priority Encoder multiple external masters
could be connected. The PCI bus clock is always sourced from the MPC5200B.
Table 10-14. XL Bus:IP:PCI Clock Ratios
XL Bus:IP:PCI
XL Bus
CLK
IP CLK PCI CLK
4:4:2 132 MHz 132 MHz 66 MHz
4:4:1 132 MHz 132 MHz 33 MHz
4:2:2 132 MHz 66 MHz 66 MHz
4:2:1 132 MHz 66 MHz 33 MHz
2:2:2 66 MHz 66 MHz 66 MHz
2:2:1 66 MHz 66 MHz 33 MHz
2:1:1 66 MHz 33 MHz 33 MHz