Freescale Semiconductor MPC5200B - Manual (Page 721)

MPC5200B Users Guide, Rev. 1
20-42 Freescale Semiconductor
Functional Description
The user begins initiation of a Type 3 IFR, as with each of the other IFR types, by loading the desired IFR byte into the BDLC Data
Register. If a byte has already been written into the BDLC Data Register for transmission as a new message, the user can simply
write the first IFR byte to the BDLC Data Register, replacing the previously written byte. This must be done before the first EOD
symbol is received.
— Step 2: Set the TMIFR Bit
The second step necessary for transmitting a Type 3 IFR is to set the desired TMIFR bit in BDLC Control Register 2, depending
upon whether or not a CRC is desired. As previously described in
Section 20.8.6.2, BDLC IFR Transmit Control Bits , the TMIFR1
bit should be set if the user requires a CRC byte to be appended following the last byte of the Type 3 IFR, and TMIFR0 if no CRC
byte is required.
Setting the TMIFR1 or TMIFR0 bit will direct the BDLC module to transmit the byte in the BDLC Data Register as the first byte
of a single or multi-byte IFR preceded by the appropriate Normalization Bit. Once this has occurred, the BDLC State Vector Register
will reflect that the next byte of the IFR can be written to the BDLC Data Register (TDRE interrupt).
NOTE
The user must set the TMIFR1 or TMIFR0 bit before the EOD following the main part of the message
frame is received, or no IFR transmit attempts will be made for the current message. If another node
does transmit an IFR to this message or a reception error occurs, the TMIFR1 or TMIFR0 bit will be
cleared. If not, the IFR will be transmitted after the EOD of the next received message.
— Step 3: When TDRE is Indicated, Write the Next IFR Byte into the BDLC Data Register
When a TDRE state is reflected in the BDLC State Vector Register, the CPU writes the next IFR byte to be transmitted into the
BDLC Data Register, clearing the TDRE interrupt. This step is repeated until the last IFR byte to be transmitted is written to the
BDLC Data Register.
NOTE
As when transmitting a message, when transmitting a Type 3 IFR the user may write two, or possibly
even three of the bytes to be transmitted into the BDLC Data Register before the first RxIFR interrupt
occurs. For this reason, the user should never use receive IFR byte interrupts to control the sequencing
of IFR bytes to be transmitted.
— Step 4: Write the Last IFR Byte into the BDLC Data Register and Set TEOD
Once the last IFR byte to be transmitted is written to the BDLC Data Register, the CPU then sets the TEOD bit in BDLC Control
Register 2. Once the TEOD bit is set, after the last IFR byte written to the BDLC Data Register is transmitted onto the bus, if the
TMIFR1 bit has been set the BDLC module will begin transmitting the CRC byte, followed by an EOD. If the TMIFR0 bit has been
set, the last IFR byte will immediately be followed by the transmission of an EOD. Following the EOD, and EOF will be recognized
and the message will be complete.
If at any time during the transmission of a Type 3 IFR a loss of arbitration occurs, the TMIFR bit which is set and the TEOD bit (if
set) will be cleared, any IFR byte being transmitted will be discarded and the loss of arbitration state will be reflected in the BDLC
State Vector Register. Likewise, if an error is detected during the transmission of a Type 3 IFR the IFR control bits will be cleared,
the byte being transmitted will be discarded and the BDLC State Vector Register will reflect the detected error.
NOTE
If the Type 3 IFR being transmitted is made up of a single byte, the appropriate TMIFR bit and the
TEOD bit can be set at the same time. The BDLC module will then treat that byte as both the first and
last IFR byte to be sent.
20.8.6.7 Transmitting IFR Exceptions
This basic IFR transmitting flow can be interrupted for the same reasons as a normal message transmission. The IFR transmit process can be
adversely affected due to a loss of arbitration, an Invalid or Out of Range Symbol, or due to a transmitter underrun caused by the CPU failing
to service a TDRE interrupt in a timely fashion. For a description of how these exceptions can affect the IFR transmit process, refer to
Section
20.8.4.2, Transmitting Exceptions .