Freescale Semiconductor MPC5200B - Manual (Page 287)

MPC5200B Users Guide, Rev. 1
9-22 Freescale Semiconductor
Programmer’s Model
NOTE
Deadcycle counter is only used, if no arbitration to an other module (ATA or PCI) of the shared local
bus happens. If an arbitration happens the bus can be dirven within 4 IPB clocks by an other module.
12:13 — Reserved
14:15 DC4 Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
4 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
16:17 — Reserved
18:19 DC3 Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
3 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
20:21 — Reserved
22:23 DC2 Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
2 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
24:25 — Reserved
26:27 DC1 Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
1 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
28:29 — Reserved
30:31 DC0 Deadcycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select
0 read access and will occur in addition to any cycles which may already exist. These cycles
are to provide peripheral additional time to tri-state it's bus after a read operation. This is for
all access types.
Bits Name Description