Freescale Semiconductor MPC5200B - Manual (Page 560)

PSC Operation Modes
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 15-49
15.3.2 PSC in Codec Mode
After reset all PSCs are in UART mode. PSC1,2,3 and 6 can be put to one of the Codec modes by writing the appropriate value to the SICR
register. The other values should be initialized at the same time. During Codec mode the PSC can connect to Codec interfaces with 8, 16, 24
or 32 bit data. For all these modes the PSC can be programmed to behave as a “normal soft modem” interface, SPI, ESAI or I2S interface.
The PSC Codec supports for all these modes the master mode (PSC drive the BitClk and FrameSync signal) or slave mode (PSC receive the
BitClk and FrameSync signals) functionality. Independently from the mode (master or slave) the PSC can provide an Mclk (master clock) for
an external Codec device. This behavior eliminates the need for an external crystal for the external Codec device.
Figure 15-6 shows a
simplified block Diagram for the PSC Codec mode. The Chapter 2, Signal Descriptions shows only the PSC signal names for the “normal”
Codec mode. Table 15-77 shows the signal assignment for all PSC Code modes.
The important register to configure the PSC for Codec mode are:
• SICR register - select the Codec mode
• for master mode:
— cdm_pscX_bitclk_config - select Mclk frequency, see
Section 5.5.11, PSC1 Mclock Config Register—MBAR + 0x0228
— cdm_clock_enable_register- enable Mclk, see Section 5.5.6, CDM Clock Enable Register—MBAR + 0x0214
— CCR - select BitClk and FrameSync Frequency
— CTUR - select FrameSync width
• RFALARM , TFALARM - select the FIFO “Alarm” level
• CR register - enable or disable receiver and transmitter
• Port_config - select the right Pin-Muxing, Chapter 2, Signal Descriptions
Table 15-76. General Configuration Sequence for UART mode
Register Value Setting
CR 0x0A Disable the Tx and Rx part for configuration if the PSC was enabled by the work
before.
CSR 0xdd00 select the clock source
SICR 0x00000000
or
0x08000000
Select the UART mode
MR1 0xXX Select Error Mode, Parity Mode and the Parity Type
MR2 0xXX Select Channel Mode, Port Control and Stop-Bit Length
CTUR 0x00 set the Baud rate to 9600 with IPB clock frequency 66 MHz
CTLR 0xD7
RFALARM 0x0XXX Choose Rx FIFO “almost full” threshold level.
TFALARM 0x0XXX Choose Tx FIFO “almost empty” threshold level.
IMR 0xXXXX select the desired interrupt
Port_Config 0x00000005 Select the Pin-Muxing for UART mode for PSC1, see Chapter 2, Signal
Descriptions
CR 0x05 Enable Tx and Rx
Table 15-77. Signal Definition for all Codec Modes
Mode Signal name
“normal” Codec
ESAI
TXD RXD CLK FrameSync
I2S SDATA_out SDATA_in SCK LRCK
SPI Master MOSI MISO SCK SS
SPI Slave MISO MOSI SCK SS