Freescale Semiconductor MPC5200B - Manual (Page 306)

Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 10-9
9 Reserved
(R)
Fixed to 0. Prior to the 2.2 PCI Spec, this was the UDF (User Defined Features) Supported
bit.
1 = Supported User Defined Features
0 = Does not support UDF
10 66 MHz
Capable
(66M)
Fixed to 1. This bit indicates that the PCI controller is 66 MHz capable.
11 Capabilities
List
(C)
Fixed to 0. This bit indicates that the PCI controller does not implement the New Capabilities
List Pointer Configuration Register in DWORD 13 of the Configuration Space.
12:21 Reserved These bits are reserved.
22 Fast
Back-to-Back
Transfer Enable
(F)
The MPC5200B PCI controller does NOT support Fast Back-to-Back transactions.
Setting this bit has no effect.
23 SERR enable
(S)
This bit is an enable bit for the SERR driver. A value of zero disables the SERR driver. A
value of 1 enables the SERR driver. Note: Address parity errors are reported only if this bit
and bit 6 are 1.
This bit is programmable (read/write from both the IP bus and PCI bus Configuration
cycles).
24 Address and
Data Stepping
(St)
Fixed to 0. This bit indicates that the PCI controller never uses address/data stepping.
Initialization software should write a 0 to this bit location.
25 Parity Error
Response
(PER)
This bit controls the device’s response to parity errors. When set and a parity error is
detected, the PCI controller asserts PERR. When the bit is “0”, the device sets its Detected
Parity Error status bit (bit 0) in the event of a parity error, but does not assert PERR.
This bit is programmable (read/write from both the IP bus and PCI bus Configuration
cycles).
26 VGA Palette
Snoop Enable
(V)
Fixed to 0. This bit indicates that the PCI controller is not VGA compatible. Initialization
software should write a 0 to this bit location.
27 Memory Write
and Invalidate
Enable
(MW)
This bit is an enable for using the Memory Write and Invalidate command. When this bit is
1, MPC5200B-as-master may generate the command. When it is 0, Memory Write must be
used instead. This bit is programmable (read/write from both the IP bus and PCI bus
Configuration cycles).
28 Special Cycle
Monitor or
Ignore
(Sp)
This bit is to determine whether or not to ignore PCI Special Cycles. Since
MPC5200B-as-target does not recognize messages delivered via the Special Cycle
operation, a value of 1 should never be programmed to this register. This bit, however, is
programmable (read/write from both the IP bus and PCI bus Configuration cycles).
29 Bus Master
Enable
(B)
This bit indicates whether or not MPC5200B has the ability to serve as a master on the PCI
bus. A value of 1 indicates this ability is enabled. If MPC5200B is used as a master on the
PCI bus (via XL bus or CommBus), a 1 should be written to this bit during initialization. Even
if set to 0, a transaction initiated by an internal master (the core, BestComm) is allowed to
take place. It is meant to be read by configuration software.
This bit is programmable (read/write from both the IP bus and PCI bus Configuration
cycles).
Bits Name Description