4 repeated start, 5 clock synchronization and arbitration, Figure 18-4 – Freescale Semiconductor MPC5200B User Manual
Page 621
MPC5200B Users Guide, Rev. 1
18-4
Freescale Semiconductor
I
2
C Controller
Figure 18-4. Timing Diagram—Receiver Acknowledgement
18.2.2.4
Repeated Start
A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. The master
uses this means to communicate with another slave or with the same slave in a different mode without releasing the bus.
Various combinations of read/write formats are possible.
shows examples of:
•
the master-transmitter transmitting to a slave-receiver. The transfer direction is not changed.
•
the master reading a slave immediately after first byte. At the moment of the first acknowledge, the master-transmitter becomes a
master-receiver and the slave-receiver becomes a slave-transmitter.
•
the START condition and slave address are both repeated using the repeated START signal. This communicates with same slave in
a different mode without releasing the bus. The master transmits data to the slave first, then the master reads data from the slave by
reversing the R/
W
bit.
Figure 18-5. Data Transfer, Combined Format
18.2.2.5
Clock Synchronization and Arbitration
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2
C is a true multi-master bus; more than one master can be connected to the bus. If two or more masters try to control the bus at the same
time, a clock synchronization procedure determines the bus clock.
Since wire-AND logic is used on the SCL line, a high-to-low transition on the SCL line affects all devices connected on the bus. The devices
start counting their low period. Once a device clock goes low, it holds the SCL line low until the clock high state is reached. However, the
change of low-to-high in this device clock may not change the SCL line state if another device clock is still within its low period. Therefore,
the synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state
during this time. See
.
When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. No difference
exists between device clocks and the SCL line state. All devices start counting their high periods. The first device to complete its high period
pulls the SCL line low again.
Bit5
Bit4
Bit3
Bit6
Bit2
Bit1
Bit0(R/W)
Bit7
1
2
3
4
5
6
7
8
9
SCL
SDA by
Transmitter
SDA by
Receiver
Start
ST
A
7-bit Slave Address
0
A
Register Address
DATA
A/A
R/W
SP
From Master to Slave
From Slave to Master
ST = Start
SP = Stop
A = Acknowledge (SDA low)
A = Not Acknowledge (SDA high)
ST
7-bit Slave Address
1
A
DATA
DATA
A
R/W
SP
ST
7-bit
1
A/A
R/W
Rept
7-bit
R/W
Rept ST = Repeated Start
Slave Address
ST
Slave Address
A
DATA
A
0
A
DATA
DATA A/A SP
A