Freescale Semiconductor MPC5200B - Manual (Page 252)

Operation
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 8-19
With both SDR and DDR memory, a Read command can be issued overlapping the masked beats at the end of a previous Single Write of the
same CS; the Read command aborts the remaining (unnecessary) Write beats. With DDR memory, a Read of one CS can even overlap the
masked beats at the end of a previous Single Write of the other CS. The Write is not aborted, but the masks remain asserted. This is not possible
with SDR memory, because SDR memory cannot be read with the masks asserted.
8.4.4.6 Burst Terminate Command
SDRAMs are burst-only devices, but they provide mechanisms to truncate a burst if not all of the beats are needed. The burst terminate
command is used to truncate read bursts (SDR and DDR) and write bursts (SDR). The most recently registered read or write command prior
to the burst terminate command will be truncated. The open page which the read or write burst was terminated from remains open.
8.4.4.7 Auto Refresh Command
The Memory Controller issues Auto Refresh commands according to the ref_interval value specified in the Memory Controller Control
register. Each time the programmed refresh interval elapses, the Memory Controller issues a Precharge All Banks command followed by an
Auto Refresh command.
If a memory access is in progress at the time the refresh interval elapses, the Memory Controller schedules the refresh after the transfer is
finished; but the interval timer continues counting so that the average refresh rate is constant.
After refresh, the SDRAM is in an idle state and waits for an Active command.
8.4.4.8 Self Refresh and Power Down Commands
The Memory Controller issues either a Power Down or a Self Refresh command if the Control register cke bit is changed from asserted to
negated. If the ref_en bit of the same register is asserted when cke is negated, the controller issues a Self Refresh command; if the ref_en bit
is negated, the controller issues a Power Down command. The ref_en bit may be changed in the same register write that changes the cke bit;
the controller will act upon the new value of the ref_en bit.
Unlike an Auto Refresh, the controller does not automatically issue a Precharge command before the Self Refresh command. It is a software
responsibility to command a Precharge, using the Control register soft_pre bit, by a separate write before negating the cke bit.
The memory is reactivated from Power Down or Self Refresh mode by reasserting the cke bit.
If a normal refresh interval elapses while the memory is in Self Refresh mode, a Precharge and Auto Refresh will be performed as soon as the
memory is reactivated. If the memory is put into and brought out of Self Refresh all within a single refresh interval, the next automatic refresh
will occur on schedule.
In Self Refresh mode, the memory does not require an external clock. The MEM_CLK can be stopped for maximum power savings by
negating the Memory Controller Clock Enable bit of the CDM Clock Enable register. See
Section 5.5.6, CDM Clock Enable Register—MBAR
+ 0x0214 . If the Memory Controller clock is stopped, the refresh interval timer must be reset before the memory is reactivated (if periodic
refresh is to be resumed). The refresh interval timer is reset by negating the Control register ref_en bit. This can be done at any time while the
memory is in Self Refresh mode, before or after the Memory Controller clock is stopped/restarted, but not with the same Control register write
that negates cke; this would put the memory in Power Down mode. To restart periodic refresh when the memory is reactivated, the ref_en bit
must be reasserted; this can be done before the memory is reactivated, or in the same Control register write that cke is reasserted.
NOTE
As soon as the CKE signal is negated (set to a logical 0) a SDRAM memory device does NOT answer
any longer to any command (all its input but the CKE are ignored) until the CKE is re-asserted and a
minimum time has elapsed (as specified by the memory vendor).
8.5 Operation
8.5.1 Power-Up Initialization
The SDRAM and SDRAM MC must be initialized after power-up. SDRAM parameters may be read from an I 2 C serial EEPROM, or compiled
into the boot ROM. See Section 18, Inter-Integrated Circuit (I 2 C) if using serial EEPROM.
The steps below should be followed to initialize the memory system.
NOTE
The sequence might change slightly from device to device. Refer to the device data sheet for the most
up-to-date information. In any case of conflict between this document and the device data sheet, the
data sheet shall prevail.
Step 1. After reset is deactivated, pause for the amount of time indicated in the SDRAM specification. Usually 100 µs or 200 µs.
Step 2. Determine the number of SDRAM CS spaces. If using both CS spaces, configure GPIO_WKUP6/CS1 for CS1 mode.