Freescale Semiconductor MPC5200B - Manual (Page 569)

MPC5200B Users Guide, Rev. 1
15-58 Freescale Semiconductor
PSC Operation Modes
Figure 15-12. I2S-Data Transmission
Table 15-84 shows an example how to configure the PSC1 as I2S master. For the slave mode the bit SICR [GenClk] must be cleared and the
configuration of the CCR register can be ignored.
• use PSC1 as I2S master
• 32bit data, MSB first
• SCLK frequency 1 MHz
• FrameSync width 40 bit
• data shifted out on the falling edge of SCLK
• data transfer starts one CLK cycle after the FrameSync is active
• Frame starts with LRCK low
• set the TFALARM level to 0x010, alarm occurs if 16 byte are in the TxFIFO
• set the RFALARM level to 0x00C, alarm occurs if 12 byte space in the RxFIFO
• enable TxRDY interrupt
Table 15-84. 32-bit I2S Master Mode for PSC1
Register Value Setting
CR 0x0A Disable the Tx and Rx part for configuration if the PSC was enabled
by the work before.
SICR 0x2FE00000 Select the 32bit Codec I2S master mode, msb first, DTS1 =1
cdm_psc1_bitclk_config 0x8020 divide the f
system clock frequency from 528 to 16 MHz Mclk, see
Section 5.5.11, PSC1 Mclock Config Register—MBAR + 0x0228
cdm_clock_enable_register 0x00000020 enable Mclk, see Section 5.5.6, CDM Clock Enable Register—MBAR +
0x0214
CCR 0x270F0000 set the FrameSync width (40 bit) and SCKL frequency
RFALARM 0x000C set the RFALARM level to 0x00C
TFALARM 0x0010 set the TFALARM level to 0x010
IMR 0x0100 enable TxRDY interrupt
Port_Config 0x00000006 Select the Pin-Muxing for PSC1 Codec mode, see Chapter 2, Signal
Descriptions
CR 0x05 Enable Tx and Rx
Frame length
DTS1
start of Frame
LRCK (Frame)
SCLK (CLK)
SDATA
Data width
empty data bits until the
new data starts (zero)
start of Frame