3 lpc rx / tx fifo control register-mbar + 0x3c48, 4 lpc rx / tx fifo alarm register-mbar + 0x3c4c, Section 9-21, lpc rx/tx fifo alarm register – Freescale Semiconductor MPC5200B User Manual

Page 295: Section 9-20, lpc rx/tx fifo control register, 4 lpc rx/tx fifo alarm register—mbar + 0x3c4c

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MPC5200B Users Guide, Rev. 1

9-30

Freescale Semiconductor

Programmer’s Model

9.7.3.3

LPC Rx/Tx FIFO Control Register—MBAR + 0x3C48

9.7.3.4

LPC Rx/Tx FIFO Alarm Register—MBAR + 0x3C4C

Table 9-20. LPC Rx/Tx FIFO Control Register

msb 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R

Reserved

WFR

Reserved

GR

Reserved

W

RESET:

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 lsb

R

Reserved

W

RESET:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bits

Name

Description

0:1

Reserved

2

WFR

When bit sets, FIFO Controller assumes next data write is End of Frame (EOF).

Note: This module does not support Framing. This bit should remain low.

3:4

Reserved

5:7

GR

Granularity—bits control high “watermark” point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free bytes times 4.

000 = FIFO waits to become completely full before stopping data request.

001 = FIFO stops data request when only one long word of space remains.

8:31

Reserved

Table 9-21. LPC Rx/Tx FIFO Alarm Register

msb 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R

Reserved

W

RESET:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 lsb

R

Reserved

Alarm

W

RESET:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bits

Name

Description

0:22

Reserved

23:31

Alarm

User writes these bits to set low level “watermark”, which is the point where FIFO asserts
request for BestComm Controller data filling. Value is in bytes. For example, with Alarm = 32,
alarm condition occurs when FIFO contains 32Bytes or less. Once asserted, alarm does not
negate until high level mark is reached, as specified by FIFO control register granularity bits.

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