Freescale Semiconductor MPC5200B - Manual (Page 349)

MPC5200B Users Guide, Rev. 1
10-52 Freescale Semiconductor
Functional Description
In addition to the configurable address window mapping logic, the register interface provides a Configuration Address Register, which
provides the ability to generate Configuration, Interrupt Acknowledge and Special Cycles. External PCI devices should be configured through
this interface.
Section 10.4.4.2, Configuration Mechanism for configuration, interrupt acknowledge, and special cycle command support.
The PCI XL Bus Initiator interface supports all XL Bus transactions, including single-beat transfers and bursts (32 bytes). Single-beat 64-bit
data transactions are automatically translated into 2-beats burst transfers on the PCI bus. Standard XL bus burst transactions are supported as
well, however, buffering is implemented to boost performance during writes and avoid deadlock scenario for all reads and memory writes. If
the target for an XL bus read from PCI disconnects part way through the burst, MPC5200B may have to handle a local memory access from
an alternate PCI master before the disconnected transfer can continue.
XL Bus initiator read requests are decoded into four types: PCI Memory, I/O, Configuration, and Interrupt Acknowledge. The PCI Controller
must first gain access to the PCI bus before acknowledging the XL Bus read request. The specific timing of the address acknowledge is
dependent upon the type of transfer.
When the XL bus requests burst data from PCI space, the data received from PCI is stored in a buffer until all requested data has been latched.
The PCI Controller does not terminate the address tenure of the XL Bus transaction until all requested data is latched. This is because PCI
targets are allowed to disconnect in the middle of a transfer, and the XL bus requires burst transfers to be atomic. If the PCI target disconnects
in the middle of the data transfer and an alternate PCI master acquires the bus and initiates a local memory access, the Controller retries the
internal read transaction on the XL bus. The PCI Controller continues to request mastership of the PCI bus until the original request is
completed.
For example, if the XL bus initiates a burst read, and the PCI target disconnects after transferring the first half of the burst, MPC5200B
re-arbitrates for the PCI bus, and when granted, initiates a new transaction with the address of the third beat of the burst (4-beat XL Bus bus
bursts). If an alternate PCI master requests data from local memory while the PCI Controller is waiting for the PCI bus grant, the PCI controller
retries the XL Bus bus transaction to allow the PCI-initiated transaction to complete and the read buffer will be emptied.
PCI critical-word-first (CWF) burst operation (i.e. cache line wrap burst) is supported and the 2-bit cache line wrap address mode is driven
on the address bus when the XL Bus bus starts the burst at a non-zero-word-first address. Note that this option is only provided as a means to
support memory targets that support cache-line wrap.
NOTE
A processor is not permitted to cache from any external memory targets residing on the PCI bus. This
was allowed previously in the PCI spec. 2.1. The PCI spec. 2.2. took this requirements away.
XL bus writes are decoded into PCI memory, PCI I/O, PCI configuration, or special cycles. If the transaction decodes into an I/O,
configuration, or special cycle, the write is connected. The PCI controller gains access to the PCI bus and successfully transfers the data before
it asserts address acknowledge to the XL bus. If the address maps to PCI memory space, the XL Bus address tenure is immediately
acknowledged and write data is posted.
A 32-byte buffer is used to post memory writes from XL Bus to PCI. Buffering minimizes the effect of the slower PCI bus on the higher-speed
XL bus. It may contain single-beat XL Bus write transactions or a single burst. After the XL bus write data is latched internally, the bus is
available for subsequent transactions without having to wait for the write to the PCI target to complete. If a subsequent XL Bus write request
to the PCI bus comes in, the data transfer is delayed until all previous writes to the PCI bus are completed. Only when the write buffer is empty
can burst data from the XL bus be posted.
10.4.4.1 Endian Translation
The PCI bus is inherently little endian in its byte ordering. The internal XLB bus, however, is big endian. XLB bus transactions are limited to
1, 2, 3, 4, 5, 6, 7, 8, or 32 byte (burst) transactions within the data bus byte lanes on any 32-bit address boundary for burst transfers.
Table 10-7
shows the byte lane mapping between the two buses.
Table 10-7. XLB bus to PCI Byte Lanes for Memory
a
Transactions
XL bus PCI Bus
A
[29:31]
TSIZ
[0:2]
Data Bus Byte Lanes
AD
[2:0]
BE
[3:0]
31:2
4
23:1
6
15:8 7:0
0 1 2 3 4 5 6 7
000 001 OP7 -- -- -- -- -- -- -- 000 1110 -- -- -- OP7
001 001 -- OP7 -- -- -- -- -- -- 000 1101 -- -- OP7 --
010 001 -- -- OP7 -- -- -- -- -- 000 1011 -- OP7 -- --
011 001 -- -- -- OP7 -- -- -- -- 000 0111 OP7 -- -- --
100 001 -- -- -- -- OP7 -- -- -- 100 1110 -- -- -- OP7