Freescale Semiconductor MPC5200B - Manual (Page 473)

MPC5200B Users Guide, Rev. 1
14-8 Freescale Semiconductor
FEC Memory Map and Registers
14.4.2 MIB Block Counters Memory Map
Table 14-8 defines the MIB Counters memory map which defines the MIB RAM space locations where hardware-maintained counters reside.
These fall in the 3200-33FF address range. Counters are divided into two groups.
1. RMON counters—are included which cover Ethernet statistics counters defined in RFC 1757. In addition to Ethernet statistics
group counters, a counter is included to count truncated frames as FEC only supports frame lengths up to 2047bytes. RMON
counters are implemented independently for Tx and Rx, to ensure accurate network statistics when operating in full-duplex mode.
2. IEEE counters—are included which support the mandatory and recommended counter packages defined in Section 5 of
ANSI/IEEE Standard 802.3 (1998 edition). FEC supports IEEE Basic Package objects, but does not require MIB block counters.
In addition, some recommended package objects supported do not require MIB counters. Counters for Tx and Rx full-duplex flow
control frames are included.
144 X_WMRK Transmit FIFO Watermark
148-180 Reserved
184 RFIFO_DATA Receive FIFO Data
188 RFIFO_STATUS Receive FIFO Status
18C RFIFO_CONTROL Receive FIFO Control
190 RFIFO_LRF_PTR Receive FIFO Last Read Frame Pointer
194 RFIFO_LWF_PTR Receive FIFO Last Write Frame Pointer
198 RFIFO_ALARM Receive FIFO Alarm Pointer
19C RFIFO_RDPTR Receive FIFO Read Pointer
1A0 RFIFO_WRPTR Receive FIFO Write Pointer
1A4 TFIFO_DATA Transmit FIFO Data
1A8 TFIFO_STATUS Transmit FIFO Status
1AC TFIFO_CONTROL Transmit FIFO Control
1B0 TFIFO_LRF_PTR Transmit FIFO Last Read Frame Pointer
1B4 TFIFO_LWF_PTR Transmit FIFO Last Write Frame Pointer
1B8 TFIFO_ALARM Transmit FIFO Alarm Pointer
1BC TFIFO_RDPTR Transmit FIFO Read Pointer
1C0 TFIFO_WRPTR Transmit FIFO Write Pointer
1C4 RESET_CNTRL Reset Control
1C8 XMIT_FSM Transmit FSM
1CC-1FF
Table 14-7. CSR Counters
Address Mnemonic Name