7 bdlc control register (dlcscr) - mbar + 0x130c, 8 bdlc status register (dlcbstat) - mbar + 0x130d, Bdlc control register (dlcscr) - mbar + 0x130c -15 – Freescale Semiconductor MPC5200B User Manual
Page 694: Bdlc control register -15
Memory Map and Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
20-15
20.7.3.7
BDLC Control Register (DLCSCR) - MBAR + 0x130C
The following register enables the BLDC module.
READ: any time
WRITE: any time
BDLCE
—
BDLC Enable (Bit 4)
This bit serves as a mux interface clock (f
bdlc
) enable/disable for power savings.
1 = The mux interface clock (f
bdlc
) and BDLC module are enabled to allow J1850 communications to take place.
0 = The mux interface clock (f
bdlc
) is disabled, shutting down the BDLC module for power saving. Bus clocks are still running
allowing registers to be accessed.
BREAK
—
send BREAK signal (Bit 0)
This bit determines whether the BDLC module will generate a BREAK symbol.
1 = The BDLC module will immediately send a Break signal on the bus, regardless of its current transmit or receive status.
0 = The BDLC module does not generate a BREAK symbol.
After setting the BREAK bit it will automatically be cleared after two IPB clock cycles.
The active Break signal causes any other transmitting module to stop transmitting immediately because it loses arbitration. It is at least 280
µs long.
When the BDLC is operating at the high bus speed all 4X symbol times are one fourth that shown, except for Break, which will be transmitted
the same length in 1X or 4X mode.
20.7.3.8
BDLC Status Register (DLCBSTAT) - MBAR + 0x130D
This register Indicates the status of the BLDC module.
Table 20-9. BDLC Rate Selection for Binary Frequencies [CLKS = 1]
IP bus clock frequency
R[7:0]
division
f
bdlc
f
CLOCK
=1.048576 MHz
$00
1
1.048576 MHz
Table 20-10. BDLC Rate Selection for Integer Frequencies [CLKS = 0]
IP bus clock frequency
R[7:0]
division
f
bdlc
f
CLOCK
=132.00000 MHz
$83
132
1.000000 MHz
f
CLOCK
=66.00000 MHz
$41
66
1.000000 MHz
f
CLOCK
=54.00000 MHz
$35
54
1.000000 MHz
f
CLOCK
=33.00000 MHz
$20
33
1.000000 MHz
f
CLOCK
=27.00000 MHz
$1A
27
1.000000 MHz
Table 20-11. BDLC Control Register
msb 0
1
2
3
4
5
6
7 lsb
R
0
0
0
BDLCE
0
0
0
BREAK
W
RESET:
0
0
0
0
0
0
0
0
= Unimplemented