2 control register-mbar + 0x0104 – Freescale Semiconductor MPC5200B User Manual
Page 255
MPC5200B Users Guide, Rev. 1
8-22
Freescale Semiconductor
Memory Controller Registers (MBAR+0x0100:0x010C)
8.7.2
Control Register—MBAR + 0x0104
The 32-bit read/write Control register controls specific operations and generates some SDRAM commands. This register is reset only by a
power-up reset signal.
Table 8-6. Memory Controller Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
mode
_en
cke
ddr
ref
_en
Rsvd
hi_
addr
Rsvd
drive
_rule
ref_interval[0:5]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
mem_
ps
Rsvd
dqs_oe
Reserved
Rsvd
W
soft
_ref
soft
_pre
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0
mode_en
0 Mode register locked, cannot be written.
1 Mode register enabled, can be written.
1
cke
0 MEM_CLK_EN negated (low).
1 MEM_CLK_EN asserted (high).
cke must be set to 1 to perform normal read and write operations. Set cke to 0 to put the
memory in Self Refresh or Power Down mode.
2
ddr
0 SDR mode.
1 DDR mode.
3
ref_en
0 Automatic refresh disabled.
1 Automatic refresh enabled.
In general, refresh must be enabled, unless the system is known to access memory in a
pattern that is guaranteed to open every row in every bank within every refresh period
t
REF
. Some memory data sheets do not spec t
REF
, but spec t
REFI
instead. In this case, t
REF
= t
REFI
x #rows.
NOTE: The number of Refresh commands required in t
REF
is #rows; if refresh is disabled,
the number of Read/Write commands required in t
REF
is #rows x 4banks.
4:6
—
Reserved
7
hi_addr
Control the use of internal address bits XLA[4:7] as row or column bits on the MEM_MA
bus. See
Table 8-7
.
8
—
Reserved (must be written 0)
9
drive_rule
0 “Tri-state except to write” mode: MPC5200B drives the MDQ and MDQS lines only
when necessary to perform write commands.
1 “Drive except to read” mode: MPC5200B tri-states the MDQ and MDQS lines only
when necessary to perform read commands.
“Drive except to read” mode prevents unterminated memory signals from floating for
extended periods. However, terminated routing is always recommended over
unterminated.