Freescale Semiconductor MPC5200B - Manual (Page 386)

ATA Host Controller Operation
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 11-21
udma_t2cyc is another special case. Unlike the name implies, this register does not control 2 UDMA timing cycles. Rather, it
controls how long the host continues to accept data after it has de-asserted HDMARDY–. According to the ATA-4 specification—if
tSR is met, the host should accept 0–1 more data words, or if tSR is exceeded, 0–2 more data words. A safe value to ensure the host
accepts these data words after HDMARDY– de-asserts is:
1. Write the calculated count in the timing registers provided in the ATA host register memory map.
2. Write ATA drive registers per ATA-4 specification using Host Controller register memory map to the setup drive for desired
operation.
3. Read/Write to unimplemented registers or read of a write-only or vice versa errors set flag bits in the ATA Host Controller status
register. The status register is cleared by writing 1 to the flag bit set to indicate an error.
4. Write ata_dma_mode register to indicate UDMA/DMA READ/WRITE operations for UDMA/DMA data transfer modes.
5. Initiate and complete data transfers according to protocols described in ATA-4 specification.
ATA host hardware does data transfers per chosen protocol. Hardware also maintains proper handshaking with the MPC5200B system.
The ATA state machine is a combination of several small state machines. The data transfers is initiated by the software. The software chooses
the mode of operation and sets up needed registers in the ATA Host Controller IPBI module.
The ATA drive registers are also set up by the software through ATA IPBI module using PIO mode. The ATA drive command and control
block registers are mapped into ATA Host Controller register memory map.
The software writes a command to be executed in the ATA drive command register. The command code is decoded by the drive electronics.
The software, at the same time indicates to the host if UDMA/DMA protocol is used for READ/WRITE of the data. This is done by setting
proper bits in the ata_dma_mode register in the ATA IPBI module.
11.4.1 PIO State Machine
In the ATA-4 spec, 16 timing characteristics must be met for a PIO data or register access:
• 9 are driven by the ATA drive controller—2 (t1 and ta) are counted by the Host Controller for checking/latching purposes.
• 7 are driven by the ATA Host Controller
To simplify Host Controller design, the following implementation is used:
• Counter—The counter used to count this timing spec (pio_<name>_counter). All non-zero counters count down from an initial
value to 1 (end)
• Start from—Where this counter is initialized.
• Activity at end—What activity to perform when counter reaches 1
• Dependencies—When counter reaches 0, what signals must be checked before counter is finished (cleared to 0)
Table 11-31. PIO Timing Requirements
Counter Start from Activity at end Dependencies
t0 t1 go to IDLE t2=0, t2i=0, t4=0
t1 1 N/A (Use t1 instead) — —
t2 t1 Latch Read_Data IORDY_reg=1
t2i t2 — —
t3 2 N/A (Use t2 instead) — —
t4 t3 write_enable=0 —
address_enable=0 —
t5 N/A (Timing controlled by drive controller) — —
t6 N/A (Timing controlled by drive controller) — —
t6z N/A (Timing controlled by drive controller) — —
Count
4 t2CYC_sec[mode] clock_period 1 – + +
clock_period
----------------------------------------------------------------------------------------------------- =