Freescale Semiconductor MPC5200B - Manual (Page 273)

MPC5200B Users Guide, Rev. 1
9-8 Freescale Semiconductor
Modes of Operation
The MUXed mode requires external logic to latch the address during the address tenure and to decode bank selects if they are encoded. This
mode is slower than the non-MUXed mode because data and address are multiplexed in time. The supported address space is limited by the
25 address lines. In MUXed mode, LocalPlus can access up to 128 MBytes of data divided into four banks each of 32 MBytes maximum.
9.4.2.1 Address Tenure
The address is presented on the corresponding AD bus bits up to a maximum of 25bits (i.e., AD[24:0]). Smaller devices (with address ranges
at 8, 16, or 24 respectively) must use the corresponding AD bits, beginning with AD[0]. AD[0] is the least significant address bit. Regardless
of address size, the entire AD bus is driven during the address phase.
The Bank Select bits appear on AD[26] (Bank Select most significant bit) and AD[25] (Bank Select least significant bit). These bit values are
pre-programmed into the corresponding LPC control register prior to initiating an external transaction.
The TSIZ bits appear on AD[30] (TSIZ most significant bit) to AD[28] (TSIZ least significant bit). These bits are calculated and driven by
the LPC based on the internal Byte Lane enables on the IP bus.
NOTE
Only TSIZs of 1, 2, or 4 are supported.
TSIZ [0:2]/AD[30:28] are driven as follows:
001 = Transaction is 1 byte.
010 = Transaction is 2 bytes.
100 = Transaction is 4 bytes.
NOTE
Other values are invalid and should not be required by the external peripheral !
Table 9-5 describes the various combinations of TSIZ, address and byte lanes for 32 bit wide data bus.
The ALE signal is active low and remains asserted for 1 external PCI bus clocks. When active any external latch should be transparent.
AD[31] & AD[27] are unused and are driven low by the LPC during the address tenure, they are used as data lines during the data phase in
32-bit modes.
9.4.2.2 Data Tenure
During Data Tenure, the following occurs:
• In the case of a write to the peripheral, the LPC drives the indicated AD data bits.
• In the case of a read, the indicated AD bits are tri-stated by the LPC.
NOTE
AD[0] is treated as the least significant data bit. Any unused data bits (as indicated by the Data Size
field in the associated control register) are driven low by the LPC. Therefore, they should NOT be
driven by the peripheral or glue chip.
At the first PCI clock edge where the ACK input is detected as asserted, the LPC terminates the transaction and releases the bus on the next
PCI Bus clock. AD bus control reverts to the PCI Controller, which is then responsible for driving default values on the bus. Obviously, any
peripheral device must tri-state the AD bus when it is not in use.
Table 9-5. Muxed Aligned Data Transfers
Transfer Size TSIZ[0:2] AD[1:0]
Data lanes
AD[31:24] AD[23:16] AD[15:8] AD[7:0]
1 Byte 001 00 Data -- -- --
01 -- Data -- --
10 -- -- Data --
11 -- -- -- Data
2 Bytes 010 00 Data Data -- --
10 -- -- Data Data
4 Bytes 100 00 Data Data Data Data