Freescale Semiconductor MPC5200B User Manual

Page 270

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Modes of Operation

MPC5200B Users Guide, Rev. 1

Freescale Semiconductor

9-5

NOTE

The 24-bit data width is not supported.

The total pin number requires also the addition of the control signals CS,
R/W, ACK, OE, TS (MOST/Graphis and Large Flash mode) and TSIZ (MOST/Graphics mode) where available.
The total supported memory size has been calculated taking into account that when accessing 16/32 bit devices A1 and/or
A0 can NOT be used.

The above options defined as BOOT Option are selectable via the reset configuration word. Other configurations are possible via software
configuration (e.g., 8-bit data and 16-bit address).

Figure 9-4

shows the operation of Non-MUXed Read/Write accesses.

TSIZ bits are available in all non-muxed modes. They appear on GPIO_WKUP_7 (TSIZ most significant bit, TSIZ 1) and TEST_SEL_1
(TSIZ least significant bit, TSIZ 2), if the LPTZ bit is set in the GPS Port Configuration Register—MBAR + 0x0B00. Only TSIZEs of 1, 2,
or 4 are supported.

TSIZ[1:2] are driven as follows:

01 = Transaction is 1 byte.

10 = Transaction is 2 bytes.

00 = Transaction is 4 bytes.

Other values are invalid and should not be required by the external peripheral!

Table 9-3

describes the various combinations of TSIZ, address and byte lanes for MOST/Graphis mode.

Table 9-2. Non-Muxed Mode Options

Category

Address Size

Data Size

Pins used Memory size

Comments

Small

8

8

16

256 Bytes

Legacy Mode

Small

8

16

24

256 Bytes

Legacy Mode

Small

16

8

24

64 kBytes

Legacy Mode

Small

16

16

32

64 kBytes

Legacy Mode (BOOT OPTION)

Medium

24

8

32

16 MBytes

Legacy Mode (BOOT OPTION)

MOST/G

24

32

56

16 MBytes

MOST Graphics (BOOT OPTION)

Burst support. No PCI or ATA support

Large

26

8

34

64 MBytes

Large Flash Mode (BOOT OPTION). Burst
support. No PCI support.

Large

26

16

42

64 MBytes

Large Flash Mode (BOOT OPTION) Burst
support. No PCI support

Table 9-3. Non-Muxed Aligned Data Transfers

Transfer Size

TSIZ[1:2]

Addr[1:0]

Data lanes

AD[31:24]

AD[23:16]

AD[15:8]

AD[7:0]

1 Byte

01

00

Data

--

--

--

01

--

Data

--

--

10

--

--

Data

--

11

--

--

--

Data

2 Bytes

10

00

Data

Data

--

--

10

--

--

Data

Data

4 Bytes

00

00

Data

Data

Data

Data

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