Freescale Semiconductor MPC5200B - Manual (Page 604)

SPI Registers—MBAR + 0x0F00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 17-3
The SS pin is the mode fault input when the SPI is in master mode and the associated data direction bit is clear. When the data direction bit is
clear and SSOE = 1, the SS pin is a general-purpose input.
SS is always an input when the SPI is in slave mode, regardless of the state of the data direction bit for that pin. When the SPI is configured
as a slave, the MISO (or SISO) output driver is three-stated until enabled by the slave select input (low true) so that many slaves may be
wire-ORed to the same MISO (or SISO) line.
The directions of the MOSI and MISO pins are also determined by the serial pin control (SPC[0]) bit.
17.3 SPI Registers—MBAR + 0x0F00
This section gives a detailed description of memory and accessible registers.
These registers are located at an offset from MBAR of 0x0F00. Register addresses are relative to this offset. Therefore, the actual register
address is:
MBAR + 0x0F00 + register address
Reads from a non-implemented address returns zeros, writes to a non-implemented address has no effect.
Hyperlinks to the SPI registers are provided below:
17.3.1 SPI Control Register 1—MBAR + 0x0F00
• SPI Control Register 1 (0x0F00) • SPI Data Register (0x0F09)
• SPI Control Register 2 (0x0F01) • SPI Port Data Register (0x0F0D)
• SPI Baud Rate Register (0x0F04) • SPI Data Direction Register (0x0F10)
• SPI Status Register (0x0F05)
Table 17-2. SPI Control Register 1
msb 0 1 2 3 4 5 6 7 lsb
R SPIE SPE SWOM
(unused)
MSTR CPOL CPHA SSOE LSBFE
W
RESET: 0 0 0 0 0 1 0 0
Bit Name Description
0 SPIE SPI Interrupt Enable—bit enables SPI interrupts each time the SPIF or MODF status flag is set.
0 = SPI interrupts disabled
1 = SPI interrupts enabled
1 SPE SPI System Enable—bit enables the SPI system and dedicates SPI port pins 3–0 to SPI
functions. When SPE is clear, the SPI system is initialized, but in a low-power disabled state.
0 = SPI system is in a low-power, disabled state
1 = SPI port pins 3–0 are dedicated to SPI functions
2 SWOM Unused
3 MSTR SPI Master/Slave Mode Select bit
0 = Slave mode
1 = Master mode
4 CPOL SPI Clock Polarity—bit selects an inverted or non-inverted SPI clock. To transmit data between
SPI modules, the SPI modules must have identical CPOL values
0 = Active-high clocks selected; SCK idles low
1 = Active-low clocks selected; SCK idles high
5 CPHA SPI Clock Phase—bit is used to shift the SCK serial clock.
0 = The first SCK edge is issued one-half cycle into the 8-cycle transfer operation
1 = The first SCK edge is issued at the beginning of the 8-cycle transfer operation