Freescale Semiconductor MPC5200B - Manual (Page 612)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 17-11
Figure 17-3. SPI Clock Format 0 (CPHA = 0)
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI Data Register is not transmitted,
instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time ( half SCK cycle) between successive
transmissions content of the SPI Data Register is transmitted.
In master mode, with slave select output enabled the SS line is always deasserted and reasserted successive transfers for at least minimum idle
time.
17.4.4.3 CPHA = 1 Transfer Format
Some peripherals require the first SCK edge before the msb becomes available at the data out pin; the second edge clocks data into the system.
In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation.
The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer
its most significant data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave.
When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB of the SPI shifter. After this
edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pins on the slave.
This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on
odd numbered edges.
Data reception is double buffered; data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI
data register after the last bit is shifted in.
After the 16th SCK edge:
• Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data
register of the slave is in the master.
• The SPIF flag bit in SPISR is set and the clock is stopped, indicating that the transfer is complete.
Table 17-4 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram since the SCK,
MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI
t
L
Begin End
SCK (CPOL = 0)
SAMPLE I
CHANGE O
SEL SS (O)
Transfer
SCK (CPOL = 1)
MSB first (LSBFE = 0):
LSB first (LSBFE = 1): MSB
LSB
LSB
MSB
Bit 5
Bit 2 Bit 6
Bit 1 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6
CHANGE O
SEL SS (I)
MOSI pin
MISO pin
Master only
MOSI/MISO
t
T
If ne
xt tr
ansf
e
r beg
ins here
for t
T
, t
l
, t
L
Minimum 1/2 SCK
t
I
t
L
t
L
= Minimum leading time before the first SCK edge
t
T
= Minimum trailing time after the last SCK edge
t
I
= Minimum idling time between transfers (minimum SS high time)
t
L
, t
T
, and t
I
are guaranteed for the master mode and required for the slave mode.